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Tue, 25 Aug 2026 18:30:29 -0700 (PDT) From: Yuanshen Cao Date: Wed, 26 Aug 2026 01:30:07 +0000 Subject: [PATCH v4 5/5] dmaengine: sun6i-dma: Add support for Allwinner A733 DMA controller Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: 7bit Message-Id: <20260826-sun60i-a733-dma-v4-5-dc2f745f40dc@gmail.com> References: <20260826-sun60i-a733-dma-v4-0-dc2f745f40dc@gmail.com> In-Reply-To: <20260826-sun60i-a733-dma-v4-0-dc2f745f40dc@gmail.com> To: Vinod Koul , Frank Li , Chen-Yu Tsai , Jernej Skrabec , Samuel Holland , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Maxime Ripard Cc: Yuanshen Cao , dmaengine@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-sunxi@lists.linux.dev, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org X-Mailer: b4 0.16.0 Implement support for the Allwinner A733 DMA controller by defining A733-specific register offsets, bitfield masks, and the `sun60i_a733_dma_cfg` configuration structure. This includes the IRQ stride, offsets, and channel counts specific to the A733, as well as the 32G mask for high-address fields in the LLI. Add `sun60i_a733_dma_cfg`, which ties all the refactored functionality together for A733. Signed-off-by: Yuanshen Cao --- drivers/dma/sun6i-dma.c | 30 ++++++++++++++++++++++++++++++ 1 file changed, 30 insertions(+) diff --git a/drivers/dma/sun6i-dma.c b/drivers/dma/sun6i-dma.c index b96d7d90f6b5..fb371b57d792 100644 --- a/drivers/dma/sun6i-dma.c +++ b/drivers/dma/sun6i-dma.c @@ -57,10 +57,14 @@ * Interrupts specific registers */ #define DMA_IRQ_STRIDE_A31 0x04 +#define DMA_IRQ_STRIDE_A733 0x40 #define DMA_IRQ_EN_OFFSET_A31 0x00 +#define DMA_IRQ_EN_OFFSET_A733 0x134 #define DMA_IRQ_STAT_OFFSET_A31 0x10 +#define DMA_IRQ_STAT_OFFSET_A733 0x138 #define DMA_IRQ_CHAN_NR_A31 8 +#define DMA_IRQ_CHAN_NR_A733 1 /* * Channels specific registers @@ -110,6 +114,8 @@ */ #define SRC_HIGH_ADDR_MASK GENMASK(17, 16) #define DST_HIGH_ADDR_MASK GENMASK(19, 18) +#define SRC_HIGH_ADDR_32G_MASK GENMASK(13, 11) +#define DST_HIGH_ADDR_32G_MASK GENMASK(17, 15) /* * Various hardware related defines @@ -1321,6 +1327,29 @@ static struct sun6i_dma_config sun50i_h6_dma_cfg = { SUN6I_DMA_IRQ_A31_COMMON_CFG }; +/* + * The A733 binding uses the number of dma channels from the + * device tree node. + */ +static struct sun6i_dma_config sun60i_a733_dma_cfg = { + .clock_autogate_enable = sun6i_enable_clock_autogate_h3, + .src_burst_lengths = BIT(1) | BIT(4) | BIT(8) | BIT(16), + .dst_burst_lengths = BIT(1) | BIT(4) | BIT(8) | BIT(16), + .src_addr_widths = BIT(DMA_SLAVE_BUSWIDTH_1_BYTE) | + BIT(DMA_SLAVE_BUSWIDTH_2_BYTES) | + BIT(DMA_SLAVE_BUSWIDTH_4_BYTES), + .dst_addr_widths = BIT(DMA_SLAVE_BUSWIDTH_1_BYTE) | + BIT(DMA_SLAVE_BUSWIDTH_2_BYTES) | + BIT(DMA_SLAVE_BUSWIDTH_4_BYTES), + .src_high_addr_mask = SRC_HIGH_ADDR_32G_MASK, + .dst_high_addr_mask = DST_HIGH_ADDR_32G_MASK, + .has_mbus_clk = true, + .irq_stride = DMA_IRQ_STRIDE_A733, + .irq_en_offset = DMA_IRQ_EN_OFFSET_A733, + .irq_stat_offset = DMA_IRQ_STAT_OFFSET_A733, + .num_channels_per_reg = DMA_IRQ_CHAN_NR_A733, +}; + /* * The V3s have only 8 physical channels, a maximum DRQ port id of 23, * and a total of 24 usable source and destination endpoints. @@ -1355,6 +1384,7 @@ static const struct of_device_id sun6i_dma_match[] = { { .compatible = "allwinner,sun50i-a64-dma", .data = &sun50i_a64_dma_cfg }, { .compatible = "allwinner,sun50i-a100-dma", .data = &sun50i_a100_dma_cfg }, { .compatible = "allwinner,sun50i-h6-dma", .data = &sun50i_h6_dma_cfg }, + { .compatible = "allwinner,sun60i-a733-dma", .data = &sun60i_a733_dma_cfg }, { /* sentinel */ } }; MODULE_DEVICE_TABLE(of, sun6i_dma_match); -- 2.55.0