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[103.229.18.19]) by smtp.gmail.com with ESMTPSA id 006d021491bc7-6b1a24bce78sm4253171eaf.3.2026.08.27.09.38.08 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 27 Aug 2026 09:38:17 -0700 (PDT) From: Hardeep Sharma Subject: [PATCH v4 00/15] Add initial support for Qualcomm Kuno SoC Date: Thu, 27 Aug 2026 22:08:01 +0530 Message-Id: <20260827-kuno-soc-support-v4-0-dd34f235fc1a@oss.qualcomm.com> Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: 7bit X-B4-Tracking: v=1; b=H4sIAOlnkGoC/33NQQ6CMBAF0KuYri2ZtljAlfcwLqAMWhWKHSAaw t0tuHGBbib5yZ/3R0boLRLbb0bmcbBkXRNCvN0wc8mbM3JbhswkSA0pZPzWN46TM5z6tnW+46L Mi1TqEqGoWHhrPVb2uZDH0ydTX1zRdLMzNy6WOudfy+Yg5t4ffhAc+A4BS4xzMIk8OKLo0ed34 +o6CofNK4P8ckS84sjgKEiyJIsrqBL1w1FfjhQrjgqOyDTKQoFWOl1xpml6A56YQ1FZAQAA X-Change-ID: 20260809-kuno-soc-support-1dab826de0bf To: Bjorn Andersson , Konrad Dybcio , Krzysztof Kozlowski , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Ulf Hansson , Michael Turquette , Stephen Boyd , Brian Masney , Georgi Djakov , Bartosz Golaszewski , Linus Walleij , Thomas Gleixner , Radu Rendec , Robert Marko , Guru Das Srinagesh , Taniya Das Cc: linux-arm-msm@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, linux-pm@vger.kernel.org, linux-clk@vger.kernel.org, linux-gpio@vger.kernel.org, Hardeep Sharma , Mukesh Savaliya , Abel Vesa , Konrad Dybcio , Dmitry Baryshkov , Bartosz Golaszewski X-Mailer: b4 0.15-dev-47773 X-Developer-Signature: v=1; a=ed25519-sha256; t=1787848688; l=7023; i=hardeep.sharma@oss.qualcomm.com; s=20260204; h=from:subject:message-id; bh=IuLBCG8fwivf7QD/EPSNHEsGg4a/dKCd3dCzYHyww5A=; b=6B8BxUlMPUMsylsRHyitMa2Od5NzIDaznMlx51zPqCnskxQq1AOXN9Rq2cA5EasT28/SZXnyU iIQVr+Htp39AP7H9U2SQA67oKpJF9KYlSBsxh3K6AjTcRH4PqFrofAH X-Developer-Key: i=hardeep.sharma@oss.qualcomm.com; a=ed25519; pk=IvwPDKA2xr6jWaCIBBY2ran/H0124QUzVfun+CtEikM= X-Proofpoint-Spam-Info: AW1haW4tMjYwODI3MDE0MCBTYWx0ZWRfXzp6n3l9++GFX w3IVYz3ja6SkzTeRPEBdzb8Vp3CqwTUIbTOAUfiKVJZoiWcx2AyR7XIHSotzpZ6W8bQZTuHhxr0 XydWDTuwgeM33wuBstEjsSzPrveG2Bg= X-Proofpoint-ORIG-GUID: 1WNM9yaslcWjaDCmRYzxbXg-hXbtMy-V X-Proofpoint-GUID: 1WNM9yaslcWjaDCmRYzxbXg-hXbtMy-V X-Authority-Analysis: v=2.4 cv=G+Ms1dk5 c=1 sm=1 tr=0 ts=6a9067fb cx=c_pps a=z9lCQkyTxNhZyzAvolXo/A==:117 a=Ou0eQOY4+eZoSc0qltEV5Q==:17 a=IkcTkHD0fZMA:10 a=Sv0fKeRqtYgA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=ZpdpYltYx_vBUK5n70dp:22 a=VwQbUJbxAAAA:8 a=EUspDBNiAAAA:8 a=8riaqLHWwNYsoh2d4OYA:9 a=QEXdDO2ut3YA:10 a=O8hF6Hzn-FEA:10 a=EyFUmsFV_t8cxB2kMr4A:22 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwODI3MDE0MCBTYWx0ZWRfX4vY4VaxP2bBV ccqhjD9LXCp43BohwR1/QVbu96vRpkN+8SH2XP1/F4AEBYfBxtEiYQJI2fgjk/iuxChFgU7gFOs rs9rj0Gqny1WlvV67HjF1Iaqpb9/UJuADkElNRwwccyv0AVpNIsOXUjLb8SUjSWJ/0o0xpqcpXF HrXWoSMk9v7H7jXbT+zjCcbNDAgJaGClPmZ1zPEWJ5Jy/X+94z6DYB0ZM1CL1nSxpHXWe2gi6Gf 1+ic5AOIWDJTS4JbL8M5R1KdTYogWM869WHlSFtVLXWZ/AowygRm/EbCmEE8JaPWYlADvXwUS/u 6HLHAxL3EFpdjN/TDZ2DkXK2IAF5knMcKznNA4Ocx7JfgkZQ1g73j0H8YiCzvoVd+OKloPJl2iR den7bOgpFEflqmnIGTT+q+r9veQLqekOr0wKGO9x6bXp4+gSqv/X7rXIdhpm9LVhRtkOTF4vl9O /qwt1FAiaOEoCAGvP8A== X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1176,Hydra:6.1.134,FMLib:17.12.100.49 definitions=2026-08-27_07,2026-08-27_01,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 priorityscore=1501 lowpriorityscore=0 adultscore=0 clxscore=1015 bulkscore=0 phishscore=0 spamscore=0 impostorscore=0 malwarescore=0 suspectscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2606150000 definitions=main-2608270140 This series adds initial support for the Qualcomm Kuno SoC and the Kuno IDP reference board. Kuno is a 32-bit ARM (Cortex-A7) Qualcomm platform. This series brings up the essential SoC infrastructure required to boot to a serial console: - Global Clock Controller (GCC) and RPMh clock controller - RPMh power domains - Interconnect (NoC) provider - TLMM pin controller - PDC interrupt controller and SCM firmware interface - Devicetree for the SoC and the Kuno IDP board The soc: qcom: geni-se patch allows the GENI serial engine driver to be selected on 32-bit ARM Qualcomm SoCs, which the debug UART console depends on. Signed-off-by: Hardeep Sharma --- Changes in v4: - Addressed v3 review feedback: - Registered the interconnect NoC provider from an explicit core_initcall() instead of module_platform_driver(), matching the established qcom interconnect driver convention. - Replaced the NA mux-slot placeholder with _ across the pinctrl PINGROUP table, matching the upstream qcom pinctrl convention. - Added minItems: 1 to the interconnect binding clocks property so a single clock is valid (system-noc), and aligned the binding examples with the sdx75 labelled-node style. - Added GDSC power-domain support to the Kuno GCC: the binding now defines GDSC macros and the driver registers the EMAC0, PCIe and USB20 GDSCs, so #power-domain-cells has real backing providers. - Split the cpu-idle-states phandle list so each phandle is on its own line. - Collected Acked-by / Reviewed-by tags from v3. - Link to v3: https://lore.kernel.org/all/20260821-kuno-soc-support-v3-0-196e2b306368@oss.qualcomm.com/ Changes in v3: - Addressed v2 review feedback: - Reworked the interconnect binding clocks: dropped clock-names and replaced the flexible min/maxItems list with fixed per-compatible clocks (aggre-noc: 2, system-noc: 1), required where present and disallowed otherwise, matching the sdx75/glymur shape. - Made #power-domain-cells required on the Kuno GCC binding and declared it on the SoC gcc node, since the Kuno GCC hosts GDSCs and is a power-domain provider (following qcom,sdx75-gcc); the driver's GDSC support will follow separately. - Made the GPIO65/66 QDSS CTI trig1 funcsel-3 route selectable: added a distinct qdss_cti_trig1_mire pin function (and allowed it in the TLMM binding enum), as the duplicate funcsel-2/3 entry left funcsel-3 unreachable. - Collected Acked-by / Reviewed-by tags from v2. - Link to v2: https://lore.kernel.org/all/20260814-kuno-soc-support-v2-0-3079794f0f73@oss.qualcomm.com/ Changes in v2: - Addressed v1 review feedback: - Reworked soc: qcom: geni-se commit message; dropped the Fixes: tag. - Reworded dt-bindings commit messages to the "Document X for the Qualcomm Kuno SoC" one-liner form. - Canonicalized copyright headers on interconnect binding / driver / NoC ID header to the single-line Qualcomm Technologies form. - Dropped unused from the interconnect driver. - Fixed MODULE_DESCRIPTION casing "KUNO" -> "Kuno" in the interconnect driver. - Extended interconnect binding to optionally allow up to four QoS AHB clocks (matches sdx75/glymur shape). - Cleaned up brace/space style in gcc-kuno.c to match peer clock drivers. - Reworked initial DTS: moved idle-states / domain-idle-states inside cpus{}, wrapped fixed clocks in a clocks{} container with peer node names (xo-board, sleep-clk), dropped the pcie_pipe_clk fixed-clock stub (the GCC 4th clock now uses <0> in DTS to match the sdx75 idiom; the YAML example uses a named placeholder), dropped the RPMHPD_CX power-domain reference on GCC (Kuno GCC has no GDSCs / no corner votes / no pm_runtime, so the reference was inert), and added a bootloader hand-off comment on the memory node. - Collected Acked-by / Reviewed-by tags from v1. - Link to v1: https://lore.kernel.org/all/20260809-kuno-soc-support-v1-0-5e0ede4a0c72@oss.qualcomm.com/ --- Hardeep Sharma (15): soc: qcom: geni-se: allow selection on 32-bit ARM Qualcomm SoCs dt-bindings: power: rpmpd: Document Kuno RPMh power domains pmdomain: qcom: rpmhpd: Add power domains for Kuno dt-bindings: clock: qcom,rpmhcc: Add Kuno RPMh clock controller clk: qcom: clk-rpmh: Add support for Kuno RPMh clocks dt-bindings: interconnect: Add Qualcomm Kuno NoC interconnect: qcom: Add Kuno interconnect provider driver dt-bindings: pinctrl: qcom: Add Kuno TLMM pinctrl: qcom: Add Kuno pinctrl driver dt-bindings: clock: qcom: Add Kuno Global Clock Controller clk: qcom: Add Global Clock Controller driver for Kuno dt-bindings: interrupt-controller: qcom,pdc: Add Kuno compatible string dt-bindings: firmware: qcom,scm: Document SCM on Kuno SoC dt-bindings: arm: qcom: Document Kuno IDP board ARM: dts: qcom: Add initial device tree for Kuno SoC .../devicetree/bindings/arm/qcom-soc.yaml | 4 +- Documentation/devicetree/bindings/arm/qcom.yaml | 5 + .../devicetree/bindings/clock/qcom,kuno-gcc.yaml | 52 + .../devicetree/bindings/clock/qcom,rpmhcc.yaml | 1 + .../devicetree/bindings/firmware/qcom,scm.yaml | 1 + .../bindings/interconnect/qcom,kuno-rpmh.yaml | 118 ++ .../bindings/interrupt-controller/qcom,pdc.yaml | 1 + .../bindings/pinctrl/qcom,kuno-tlmm.yaml | 110 ++ .../devicetree/bindings/power/qcom,rpmpd.yaml | 1 + arch/arm/boot/dts/qcom/Makefile | 1 + arch/arm/boot/dts/qcom/qcom-kuno-idp.dts | 25 + arch/arm/boot/dts/qcom/qcom-kuno.dtsi | 423 ++++++ drivers/clk/qcom/Kconfig | 10 + drivers/clk/qcom/Makefile | 1 + drivers/clk/qcom/clk-rpmh.c | 15 + drivers/clk/qcom/gcc-kuno.c | 1483 ++++++++++++++++++++ drivers/interconnect/qcom/Kconfig | 13 + drivers/interconnect/qcom/Makefile | 2 + drivers/interconnect/qcom/kuno.c | 988 +++++++++++++ drivers/pinctrl/qcom/Kconfig.msm | 11 + drivers/pinctrl/qcom/Makefile | 1 + drivers/pinctrl/qcom/pinctrl-kuno.c | 801 +++++++++++ drivers/pmdomain/qcom/rpmhpd.c | 16 + drivers/soc/qcom/Kconfig | 1 - include/dt-bindings/clock/qcom,kuno-gcc.h | 100 ++ include/dt-bindings/interconnect/qcom,kuno.h | 89 ++ 26 files changed, 4270 insertions(+), 3 deletions(-) --- base-commit: f82a5da2f04960df9fb57489992d03dd5e64ec6f change-id: 20260809-kuno-soc-support-1dab826de0bf Best regards, -- Hardeep Sharma