Re: [PATCH v5 15/15] ARM: dts: qcom: Add initial device tree for Kuno SoC

[sashiko-bot@kernel.org]

Thank you for your contribution! Sashiko AI review found 3 potential issue(s) to consider:
- [High] The TLMM (pinctrl) node is missing the `wakeup-parent = <&pdc>;` property.
- [High] Incorrect architected timer GIC PPI mapping and ordering.
- [Medium] The `ranges` property in the `soc` node truncates the bus mapping by one byte.
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commit 429df2d2736988037173b656c9a9508e2e6b4476
Author: Hardeep Sharma <hardeep.sharma@oss.qualcomm.com>

ARM: dts: qcom: Add initial device tree for Kuno SoC

This adds the initial device tree source and include files for the
Qualcomm Kuno SoC and IDP board. It includes initial peripheral
nodes such as PSCI, RPMh, GCC, TLMM, interconnects, and UART.

> diff --git a/arch/arm/boot/dts/qcom/qcom-kuno.dtsi b/arch/arm/boot/dts/qcom/qcom-kuno.dtsi
> new file mode 100644
> index 0000000000000..d0c6e3f21a14f
> --- /dev/null
> +++ b/arch/arm/boot/dts/qcom/qcom-kuno.dtsi
[ ... ]
> +	soc: soc@0 {
> +		compatible = "simple-bus";
> +		#address-cells = <1>;
> +		#size-cells = <1>;
> +		ranges = <0 0 0xffffffff>;

[Severity: Medium]
Does this truncate the 32-bit address space bus mapping by one byte?
A size of 0xffffffff leaves the final byte of the 4GB address space unmapped.
Should this use an empty ranges property to map the entire address space
correctly?

[ ... ]
> +		tlmm: pinctrl@f000000 {
> +			compatible = "qcom,kuno-tlmm";
> +			reg = <0x0f000000 0x400000>;
> +			interrupts = <GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH>;
> +			gpio-controller;
> +			#gpio-cells = <2>;
> +			gpio-ranges = <&tlmm 0 0 110>;
> +			interrupt-controller;
> +			#interrupt-cells = <2>;

[Severity: High]
Is the tlmm node missing the wakeup-parent property?
Without chaining the TLMM to the Power Domain Controller (pdc node) via
wakeup-parent, any GPIOs configured as wakeup sources cannot wake the system
from deep sleep states.

[ ... ]
> +	timer {
> +		compatible = "arm,armv7-timer";
> +		interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>,
> +			     <GIC_PPI 12 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>,
> +			     <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>,
> +			     <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>;
> +	};
> +};

[Severity: High]
Are these GIC PPI numbers correctly mapped and ordered?
The non-secure timer appears to be incorrectly set to PPI 12 instead of 14,
and the virtual and hypervisor interrupts (10 and 11) seem to be swapped.
This incorrect mapping will cause the kernel to request the wrong IRQs and
can lead to early boot hangs when timer interrupts fail to arrive.

-- 
Sashiko AI review · https://sashiko.dev/#/patchset/20260827-kuno-soc-support-v5-0-6d47636a8f09@oss.qualcomm.com?part=15