From: sashiko-bot@kernel.org
To: "Krishna Chaitanya Chundru" <krishna.chundru@oss.qualcomm.com>
Cc: conor+dt@kernel.org, linux-pci@vger.kernel.org,
devicetree@vger.kernel.org, linux-phy@lists.infradead.org,
vkoul@kernel.org, neil.armstrong@linaro.org, olteanv@gmail.com,
robh@kernel.org
Subject: Re: [PATCH v2 3/4] PCI: qcom: Add CGC disable workaround for Nord PCIe
Date: Fri, 28 Aug 2026 08:50:29 +0000 [thread overview]
Message-ID: <20260828085030.6BB6B1F00A3A@smtp.kernel.org> (raw)
In-Reply-To: <20260828-nord-v2-3-18bf59d19d6f@oss.qualcomm.com>
> Nord requires a workaround to address a timing convergence issue in the
> PCIe power domain. To avoid the issue, set the CORE_CLK_CGC_DIS and
> AUX_PWR_DET bits in PARF_SYS_CTRL after controller initialization.
>
> The SLV_ACLK_CGC_DIS bit is already configured by hardware reset. This
> change adds the remaining required settings as documented in
> QCTDD11972446.
>
> Signed-off-by: Krishna Chaitanya Chundru <krishna.chundru@oss.qualcomm.com>
Sashiko has reviewed this patch and found no issues. It looks great!
--
Sashiko AI review · https://sashiko.dev/#/patchset/20260828-nord-v2-0-18bf59d19d6f@oss.qualcomm.com?part=3
next prev parent reply other threads:[~2026-08-28 8:50 UTC|newest]
Thread overview: 9+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-08-28 8:43 [PATCH v2 0/4] Add PCIe support for Qualcomm Nord platform Krishna Chaitanya Chundru
2026-08-28 8:43 ` [PATCH v2 1/4] dt-bindings: phy: qcom: add Nord QMP PCIe PHY binding Krishna Chaitanya Chundru
2026-08-28 8:49 ` sashiko-bot
2026-08-28 8:43 ` [PATCH v2 2/4] dt-bindings: pci: qcom: add Nord PCIe controller compatible Krishna Chaitanya Chundru
2026-08-28 8:49 ` sashiko-bot
2026-08-28 8:43 ` [PATCH v2 3/4] PCI: qcom: Add CGC disable workaround for Nord PCIe Krishna Chaitanya Chundru
2026-08-28 8:50 ` sashiko-bot [this message]
2026-08-28 8:43 ` [PATCH v2 4/4] phy: qcom: qmp-pcie: Add Nord Gen5x16 PCIe multi-PHY support Krishna Chaitanya Chundru
2026-08-28 8:54 ` sashiko-bot
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