From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 52B1E47D956; Tue, 1 Sep 2026 12:15:43 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1788264943; cv=none; b=KUhbnWp8kXl/25+tfo3uGT8p1zwh4Bt0ZklBgNk2riSYZqYvJXR97jYaHrShy4Bn9EYKvRsAUYe9XfV5lsPMQ2mJVvdbVYO7c74kBRqnyUsCj+EoUl5Vy533Ayv2NhNaHOUAhDJxVn6ep7EGLdAqqwo4IL4fOoU/OzrlVkPgKrg= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1788264943; c=relaxed/simple; bh=aC9eTAMi0OOM2Bgn0ghZ/W4r+uPD1jhTPP9DQztf1fY=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=bKNtddTyauyMZ7JVYGvzgy/6aay5v5hSbRV47uA0GlLg9LCf3TqvFXmktcaDcEDv4/h4xucN1isHUUIRLWwwyEHlH+kK7xxWwgifpR20I8xBq2sAD/Obf6GaDG8kTfllLk5TTr3EWuRftIIF14krHLXm1HX19h3sGqUw0skYKPM= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=IY+nh25B; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="IY+nh25B" Received: by smtp.kernel.org (Postfix) with ESMTPS id 31E81C4AF55; Tue, 1 Sep 2026 12:15:43 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1788264943; bh=aC9eTAMi0OOM2Bgn0ghZ/W4r+uPD1jhTPP9DQztf1fY=; h=From:Date:Subject:References:In-Reply-To:To:Cc:Reply-To:From; b=IY+nh25BWyj12/k2Pq1ujK641uq1dPFtAg13all4CfUsAjo8bEtgSa1xx6mG0dn1k i8o6ottwuRqP8SAyOlzop6dWHthKqe+MCNGU5/jkqqQiyLJH7gD2stHFuuthzqq5S8 r7fpmC/E2QknwZ+pKb6j60FQanlUrxmgn7tSJIFXE1l6SR/2qOJW+h09Aj8wBbOOGl 7fUGuYcravYNtJbHA94A+d96Bf7tyt7HvB4+NehOTFmQ4ZndZ73v2fimV5TwRb9rcU s7K58uqdITIcAEUMoYLC/fkSLXD+4T4y8KFdlN/RHWnH/Sl7/Y/w+vdb5W55eyafNI BPDnYqHL53rhg== Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id 200FBC624D4; Tue, 1 Sep 2026 12:15:43 +0000 (UTC) From: Colin Huang via B4 Relay Date: Tue, 01 Sep 2026 20:15:24 +0800 Subject: [PATCH v7 09/11] ARM: dts: aspeed: anacapa: Add LPDB fuse monitor GPIO expander Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: 7bit Message-Id: <20260901-anacapa-devlop-phase-devicetree-v7-9-0bd71d2e0105@gmail.com> References: <20260901-anacapa-devlop-phase-devicetree-v7-0-0bd71d2e0105@gmail.com> In-Reply-To: <20260901-anacapa-devlop-phase-devicetree-v7-0-0bd71d2e0105@gmail.com> To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Joel Stanley , Andrew Jeffery , Ryan Chen , Billy Tsai Cc: devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-aspeed@lists.ozlabs.org, linux-kernel@vger.kernel.org, colin.huang2@amd.com, Colin Huang , Rex Fu X-Mailer: b4 0.14.3 X-Developer-Signature: v=1; a=ed25519-sha256; t=1788264931; l=3707; i=u8813345@gmail.com; s=20260202; h=from:subject:message-id; bh=XDe8OanyqhQtPqFNuz6nTtJf4V9+FAm+mTk0hIZBJNE=; b=BsAlKLJqtFR9ny7JLOgiDOCgCUotH4tMDowmylNEKBk2FK0agvqzmXf+gtrlXT1cL/DWwqPMv vUN7DP3OfxcDZIpyf4lRWlaiUZNfo3+7EmHfbq0tomxpxmNNB1MWwRV X-Developer-Key: i=u8813345@gmail.com; a=ed25519; pk=Zlg0WqpCw4qbswOqamTBTXIchwR/3SnYZpy7rjaGMdQ= X-Endpoint-Received: by B4 Relay for u8813345@gmail.com/20260202 with auth_id=761 X-Original-From: Colin Huang Reply-To: u8813345@gmail.com From: Rex Fu Add PCA9554 GPIO expanders for PDB fuse monitor signals on the Anacapa DVT board. The patch adds GPIO expander definitions for both the left and right PDBs under the i2c8 multiplexer and updates the associated gpio-line-names to reflect the final signal assignments. Signed-off-by: Rex Fu --- .../aspeed/aspeed-bmc-facebook-anacapa-dvt.dtsi | 92 ++++++++++++++++++++++ 1 file changed, 92 insertions(+) diff --git a/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-anacapa-dvt.dtsi b/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-anacapa-dvt.dtsi index 6650a5e4e130..cb4c41bd8b8f 100644 --- a/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-anacapa-dvt.dtsi +++ b/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-anacapa-dvt.dtsi @@ -3,6 +3,98 @@ /dts-v1/; #include "aspeed-bmc-facebook-anacapa-evt2.dtsi" +// MB - PDB +&i2c8 { + i2c-mux@72 { + i2c@0 { + gpio@22 { + gpio-line-names = + "RPDB_FAN_FULL_SPEED_R_N", "RPDB_I2C_TMP432_U8_ALERT_R_N", + "RPDB_I2C_TMP432_U29_ALERT_R_N", "RPDB_GLOBAL_WP", + "RPDB_FAN_CT_FAN_FAIL_R_N", "RPDB_VERID_A0", + "RPDB_VERID_A1", "RPDB_VERID_A2", + "RPDB_ALERT_P50V_HSC2_R_N", "RPDB_ALERT_P50V_HSC3_R_N", + "RPDB_ALERT_P50V_HSC4_R_N", "RPDB_ALERT_P50V_STBY_R_N", + "RPDB_P12V_MB_VRM_ALERT_R_N", + "RPDB_P12V_STBY_VRM_ALERT_R_N", + "RPDB_PGD_P3V3_STBY_PWRGD_R", + "RPDB_P12V_STBY_VRM_PWRGD_BUF_R"; + }; + + gpio@24 { + gpio-line-names = + "RPDB_EAM2_PRSNT_MOS_N_R", "RPDB_EAM3_PRSNT_MOS_N_R", + "RPDB_PWRGD_P50V_HSC4_SYS_R", + "RPDB_PWRGD_P50V_STBY_SYS_BUF_R", + "RPDB_P50V_FAN5_R2_PG", "RPDB_P50V_FAN6_R2_PG", + "RPDB_P50V_FAN7_R2_PG", "RPDB_P50V_FAN8_R2_PG", + "RPDB_SKU_ID0", "RPDB_FAN5_PRSNT_N_R", + "", "RPDB_FAN6_PRSNT_N_R", + "RPDB_FAN7_PRSNT_N_R", "RPDB_FAN8_PRSNT_N_R", + "", ""; + }; + + gpio@38 { + compatible = "nxp,pca9554"; + reg = <0x38>; + #gpio-cells = <2>; + gpio-controller; + + gpio-line-names = + "RPDB_P50V_FUSE2_TVS1", "RPDB_P50V_FUSE2_TVS2", + "RPDB_P50V_FUSE3_TVS1", "RPDB_P50V_FUSE3_TVS2", + "RPDB_P50V_FUSE4_TVS1", "", + "", ""; + + interrupt-parent = <&sgpiom0>; + interrupts = <174 IRQ_TYPE_LEVEL_LOW>; + }; + }; + + i2c@1 { + gpio@22 { + gpio-line-names = + "LPDB_FAN_FULL_SPEED_R_N", "LPDB_I2C_TEMP75_U8_ALERT_R_N", + "LPDB_I2C_TMP432_U29_ALERT_R_N", "LPDB_GLOBAL_WP", + "LPDB_FAN_CT_FAN_FAIL_R_N", "LPDB_VERID_A0", + "LPDB_VERID_A1", "LPDB_VERID_A2", + "LPDB_ALERT_P50V_HSC0_R_N", "LPDB_ALERT_P50V_HSC1_R_N", + "LPDB_ALERT_P50V_HSC5_R_N", "LPDB_I2C_P12V_SW_VRM_ALERT_R_N", + "LPDB_EAM0_PRSNT_MOS_N_R", "LPDB_EAM1_PRSNT_MOS_N_R", + "LPDB_PWRGD_P50V_HSC5_SYS_R", "BARKLIP_PRSNT_N_R3"; + }; + + gpio@24 { + gpio-line-names = + "LPDB_P50V_FAN0_R2_PG", "LPDB_P50V_FAN1_R2_PG", + "LPDB_P50V_FAN2_R2_PG", "LPDB_P50V_FAN3_R2_PG", + "LPDB_P50V_FAN4_R2_PG", "LPDB_FAN0_PRSNT_N_R", + "LPDB_FAN1_PRSNT_N_R", "LPDB_FAN2_PRSNT_N_R", + "LPDB_FAN3_PRSNT_N_R", "LPDB_FAN4_PRSNT_N_R", + "LPDB_SKU_ID0", "", + "", "", + "", "LPDB_PG_P3V3_R"; + }; + + gpio@38 { + compatible = "nxp,pca9554"; + reg = <0x38>; + #gpio-cells = <2>; + gpio-controller; + + gpio-line-names = + "LPDB_P50V_FUSE0_TVS1", "LPDB_P50V_FUSE0_TVS2", + "LPDB_P50V_FUSE1_TVS1", "LPDB_P50V_FUSE1_TVS2", + "LPDB_P50V_FUSE5_TVS1", "", + "", ""; + + interrupt-parent = <&sgpiom0>; + interrupts = <174 IRQ_TYPE_LEVEL_LOW>; + }; + }; + }; +}; + &sgpiom0 { gpio-line-names = /*in - out */ -- 2.34.1