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[9.244.8.156]) by smtp.gmail.com with ESMTPSA id 586e51a60fabf-46a4b7a9f82sm10697162fac.18.2026.09.01.08.07.20 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 01 Sep 2026 08:07:21 -0700 (PDT) From: Enzo Adriano To: Vinicius Pedrosa Cc: Junhui Liu , Jerome Brunet , Chen-Yu Tsai , Jernej Skrabec , Samuel Holland , Maxime Ripard , devicetree@vger.kernel.org, linux-sunxi@lists.linux.dev, linux-arm-kernel@lists.infradead.org Subject: Re: [PATCH 0/4] arm64: dts: allwinner: add A733/Cubie A7S DTS support Date: Tue, 1 Sep 2026 11:07:20 -0400 Message-ID: <20260901150720.1764626-1-enzo.adriano.code@gmail.com> X-Mailer: git-send-email 2.53.0 In-Reply-To: <20260826230942.466219-1-vinicius.eduardo.pedrosa@gmail.com> References: <20260613-a733-dts-v1-public-ready-v1-0-7787c94681db@gmail.com> <20260826230942.466219-1-vinicius.eduardo.pedrosa@gmail.com> Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Hi Vinicius, Thanks for the detailed report. I reproduced all three issues and updated the private v2 candidate. The Cubie A7S board now defines a correctly named 26 MHz `hosc`. The main CCU takes `hosc` plus `losc`, `iosc`, and `losc-fanout` from the RTC clock provider, matching the four-input binding. I also renamed the bus to `soc@0` and moved the UART0 pins into the DTSI with `allwinner,pinmux = <2>`. The MMC binding fix is already in mainline, so v2 will contain three patches instead of four. I will hold v2 until the public CCU and pinctrl prerequisites are resolved, then rebuild and retest on that public stack. Assisted-by: Codex:gpt-5 I reviewed this reply and take responsibility for its contents. Thanks, Enzo