Re: [PATCH v4 6/7] arm64: dts: renesas: add support for solidrun rzg2lc som and hb-iiot evb

[sashiko-bot@kernel.org]

Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider:
- [Medium] Incorrect memory base address in device tree: `0x40000000` instead of `0x48000000`.
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commit f502b3c798473b8b3737ee55d511455f5f7f315c
Author: Josua Mayer <josua@solid-run.com>

arm64: dts: renesas: add support for solidrun rzg2lc som and hb-iiot evb

This commit adds support for the SolidRun RZ/G2LC SoM and Hummingboard IIoT
evaluation board. It includes the device tree source for the board
components, such as memory mappings, regulators, and interfaces.

> diff --git a/arch/arm64/boot/dts/renesas/rzg2lc-sr-som.dtsi b/arch/arm64/boot/dts/renesas/rzg2lc-sr-som.dtsi
> new file mode 100644
> index 0000000000000..468304bdd47b4
> --- /dev/null
> +++ b/arch/arm64/boot/dts/renesas/rzg2lc-sr-som.dtsi

[ ... ]

> +	reserved-memory {
> +		ranges;
> +		#address-cells = <2>;
> +		#size-cells = <2>;
> +
> +		mmp_reserved: linux,multimedia@68000000 {
> +			compatible = "shared-dma-pool";
> +			reg = <0x0 0x68000000 0x0 0x8000000>;
> +			reusable;
> +		};
> +
> +		global_cma: linux,cma@58000000 {
> +			compatible = "shared-dma-pool";
> +			reg = <0x0 0x58000000 0x0 0x10000000>;
> +			reusable;
> +			linux,cma-default;
> +		};
> +	};
> +
> +	sdhi1_pwrseq: sdhi1-pwrseq {
> +		compatible = "mmc-pwrseq-simple";
> +		reset-gpios = <&pinctrl RZG2L_GPIO(23, 0) GPIO_ACTIVE_LOW>;
> +	};
> +
> +	/* 32.768kHz crystal */
> +	x2: x2-clock {
> +		compatible = "fixed-clock";
> +		#clock-cells = <0>;
> +		clock-frequency = <32768>;
> +	};
> +
> +	memory@40000000 {
> +		reg = <0x0 0x40000000 0x0 0x40000000>;

[Severity: Medium]
Is this memory base address correct? The RZ/G2L architecture typically
reserves the first 128MB of DDR (0x40000000 - 0x47FFFFFF) for the secure
area (TF-A / TrustZone enclave). If the bootloader doesn't rewrite this,
won't the kernel accessing this range trigger an SError?

Given the reserved-memory nodes at 0x58000000 and 0x68000000, should the
intended base address actually be 0x48000000?

> +		device_type = "memory";
> +	};
> +};

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Sashiko AI review · https://sashiko.dev/#/patchset/20260902-rzg2-sr-boards-v4-0-4a456a422fee@solid-run.com?part=6