Re: [PATCH v46 6/7] arm64: dts: imx8ulp: add secure enclave node

[sashiko-bot@kernel.org]

Thank you for your contribution! Sashiko AI review found 2 potential issue(s) to consider:
- [Medium] Schema violation: the 'secure-enclave' node lacks the mandatory 'memory-region' property, causing dtbs_check failures for boards that do not enable it.
- [Low] Commit message and code mismatch regarding the SRAM address label.
--

commit a07f75a4e7246d0362429146aa833aff2a0e76b4
Author: Pankaj Gupta <pankaj.gupta@nxp.com>

arm64: dts: imx8ulp: add secure enclave node

This commit adds the EdgeLock Enclave (ELE) secure-enclave node to the
i.MX8ULP SoC dtsi. It adds a label to the SRAM node and introduces the
disabled hsm0 node.

> Add the EdgeLock Enclave (ELE) secure-enclave node to the i.MX8ULP SoC
> dtsi, together with a label for sram@2201f000 that the node references.

[Severity: Low]
The commit message mentions adding a label for sram@2201f000, but the diff
actually applies the 'sram0' label to sram@22010000. Is this a typo in the
commit message, or was the wrong SRAM node labeled?

> Keep the node disabled in the SoC dtsi so it does not impose a
> reserved-memory requirement on every board. Boards enable the enclave and
> provide its memory-region by including imx8ulp-firmware.dtsi.
> 
> Signed-off-by: Pankaj Gupta <pankaj.gupta@nxp.com>
> Reviewed-by: Frank Li <Frank.Li@nxp.com>
> 
> ---
> arch/arm64/boot/dts/freescale/imx8ulp.dtsi | 12 ++++++++++--
>  1 file changed, 10 insertions(+), 2 deletions(-)
> 
> diff --git a/arch/arm64/boot/dts/freescale/imx8ulp.dtsi b/arch/arm64/boot/dts/freescale/imx8ulp.dtsi
> index 777b89ed68490..ac8293f81c6b2 100644
> --- a/arch/arm64/boot/dts/freescale/imx8ulp.dtsi
> +++ b/arch/arm64/boot/dts/freescale/imx8ulp.dtsi

[ ... ]

> @@ -154,7 +154,7 @@ sosc: clock-sosc {
>  		#clock-cells = <0>;
>  	};
>  
> -	sram@22010000 {
> +	sram0: sram@22010000 {
>  		compatible = "mmio-sram";
>  		reg = <0x0 0x22010000 0x0 0x10000>;
>  
> @@ -186,6 +186,14 @@ scmi_sensor: protocol@15 {
>  				#thermal-sensor-cells = <1>;
>  			};
>  		};
> +
> +		hsm0: secure-enclave {
> +			compatible = "fsl,imx8ulp-se-ele-hsm";
> +			mbox-names = "tx", "rx";
> +			mboxes = <&s4muap 0 0>, <&s4muap 1 0>;
> +			sram = <&sram0>;
> +			status = "disabled";
> +		};

[Severity: Medium]
Will this lack of a memory-region property cause dtbs_check validation
failures?

The fsl,imx-se.yaml binding unconditionally requires the memory-region
property for this compatible string. Because dt-schema evaluates all nodes,
even disabled ones, this will structurally conflict and cause dtbs_check to
fail for any board that includes this dtsi without also enabling the node and
providing the memory-region.

Is there a way to avoid imposing dtbs_check failures on boards that do not
configure this enclave?

-- 
Sashiko AI review · https://sashiko.dev/#/patchset/20260903-imx-se-if-v46-0-aefaab525034@nxp.com?part=6