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From: sashiko-bot@kernel.org
To: "Cristian Ciocaltea" <cristian.ciocaltea@collabora.com>
Cc: devicetree@vger.kernel.org, conor+dt@kernel.org,
	dri-devel@lists.freedesktop.org, robh@kernel.org
Subject: Re: [PATCH v4 06/14] drm/rockchip: vop2: Fix VOP2_MAX_DCLK_RATE overflow on 32-bit
Date: Wed, 02 Sep 2026 23:01:35 +0000	[thread overview]
Message-ID: <20260902230135.E54D61F00A3D@smtp.kernel.org> (raw)
In-Reply-To: <20260903-dw-hdmi-qp-yuv-v4-6-fb45bf4147eb@collabora.com>

Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider:

Pre-existing issues:
- [High] This problem wasn't introduced by this patch, but the DRM subsystem guidelines explicitly designate CRTC atomic enable and disable callbacks as executing in atomic context where sleeping is forbidden. However, `vop2_crtc_atomic_enable` and `vop2_crtc_atomic_disable` invoke multiple sleeping functions. For example, both callbacks invoke `vop2_lock()` (which acquires a mutex). `vop2_crtc_atomic_enable` calls `clk_prepare_enable()`, and `vop2_crtc_atomic_disable` calls `wait_for_completion_timeout()`.
--

commit 42f6f5bd762f8191ecc03127da51288c0ad3ea76
Author: Cristian Ciocaltea <cristian.ciocaltea@collabora.com>

drm/rockchip: vop2: Fix VOP2_MAX_DCLK_RATE overflow on 32-bit

This commit modifies the VOP2_MAX_DCLK_RATE macro to use an unsigned long 
long suffix. This ensures 64-bit arithmetic is used during clock rate 
calculations, preventing integer overflows on architectures where unsigned 
long is 32-bit.

Link: https://lore.kernel.org/all/20260623203310.9F8C81F000E9@smtp.kernel.org/

> diff --git a/drivers/gpu/drm/rockchip/rockchip_drm_vop2.c b/drivers/gpu/drm/rockchip/rockchip_drm_vop2.c
> index 12a6341e3c988..c3f72cac63690 100644
> --- a/drivers/gpu/drm/rockchip/rockchip_drm_vop2.c
> +++ b/drivers/gpu/drm/rockchip/rockchip_drm_vop2.c
> @@ -102,7 +102,7 @@ enum vop2_afbc_format {
>  	VOP2_AFBC_FMT_INVALID = -1,
>  };
>  
> -#define VOP2_MAX_DCLK_RATE		600000000UL
> +#define VOP2_MAX_DCLK_RATE		600000000ULL

[Severity: High]
This isn't a bug introduced by this patch, but while reviewing this file, I
noticed that the CRTC atomic callbacks appear to invoke sleeping functions.

In vop2_crtc_atomic_enable():

    vop2_lock(vop2);

    ret = clk_prepare_enable(vp->dclk);

And in vop2_crtc_atomic_disable():

    ret = wait_for_completion_timeout(&vp->dsp_hold_completion,
                                      msecs_to_jiffies(50));

Does this code risk system instability or deadlocks? The DRM subsystem 
guidelines designate CRTC atomic enable and disable callbacks as executing 
in an atomic context where sleeping is forbidden, yet these paths acquire a
mutex, enable clocks, and wait for completion timeouts.

-- 
Sashiko AI review · https://sashiko.dev/#/patchset/20260903-dw-hdmi-qp-yuv-v4-0-fb45bf4147eb@collabora.com?part=6

  reply	other threads:[~2026-09-02 23:01 UTC|newest]

Thread overview: 20+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2026-09-02 22:54 [PATCH v4 00/14] Support 10-bit YUV422 and 8/10-bit YUV420 color format on DW HDMI QP Cristian Ciocaltea
2026-09-02 22:54 ` [PATCH v4 01/14] dt-bindings: display: vop2: Add missing reset properties Cristian Ciocaltea
2026-09-02 22:54 ` [PATCH v4 02/14] drm/rockchip: vop2: Fix resource leak on vop2_enable() error path Cristian Ciocaltea
2026-09-02 23:03   ` sashiko-bot
2026-09-02 22:54 ` [PATCH v4 03/14] drm/rockchip: vop2: Balance state on atomic_enable() error paths Cristian Ciocaltea
2026-09-02 22:54 ` [PATCH v4 04/14] drm/rockchip: vop2: Send pending event when atomic_enable() fails Cristian Ciocaltea
2026-09-02 22:54 ` [PATCH v4 05/14] drm/rockchip: vop2: Avoid division by zero when computing max_dclk Cristian Ciocaltea
2026-09-02 22:54 ` [PATCH v4 06/14] drm/rockchip: vop2: Fix VOP2_MAX_DCLK_RATE overflow on 32-bit Cristian Ciocaltea
2026-09-02 23:01   ` sashiko-bot [this message]
2026-09-02 22:54 ` [PATCH v4 07/14] drm/rockchip: vop2: Reset AXI and DCLK to improve robustness Cristian Ciocaltea
2026-09-02 22:54 ` [PATCH v4 08/14] drm/rockchip: vop2: Avoid DCLK source switch for 10-bit YUV422 output Cristian Ciocaltea
2026-09-02 22:54 ` [PATCH v4 09/14] drm/rockchip: vop2: Consolidate HDMI PHY PLL clock parent switch Cristian Ciocaltea
2026-09-02 23:01   ` sashiko-bot
2026-09-02 22:54 ` [PATCH v4 10/14] drm/rockchip: vop2: Switch to enum vop_csc_format Cristian Ciocaltea
2026-09-02 22:54 ` [PATCH v4 11/14] drm/bridge: dw-hdmi-qp: Log resolution and refresh rate in atomic_enable() Cristian Ciocaltea
2026-09-02 22:54 ` [PATCH v4 12/14] drm/rockchip: dw_hdmi_qp: Support 10-bit YUV422 output format Cristian Ciocaltea
2026-09-02 23:06   ` sashiko-bot
2026-09-02 22:54 ` [PATCH v4 13/14] drm/rockchip: dw_hdmi_qp: Enable YUV420 " Cristian Ciocaltea
2026-09-02 23:08   ` sashiko-bot
2026-09-02 22:54 ` [PATCH v4 14/14] arm64: dts: rockchip: Add RK3588 VOP2 resets Cristian Ciocaltea

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