From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from bali.collaboradmins.com (bali.collaboradmins.com [148.251.105.195]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 6DF8543CED9; Wed, 2 Sep 2026 22:54:23 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=148.251.105.195 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1788389666; cv=none; b=qfpQDj1zfoT2sHE35XEX30h9jrWtaNB2wTfLONaoSUuO0k2Og9/azlt6JrjONGisjMtkPR8SBE0DEo68Yptw635o6QZqsZN6x65HiDFr3qNrippo8JC+D/S3O2Q6z2P+0fNEDYLSUsth12N4AX33hOzWisce6W0HsHyxv0/u600= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1788389666; c=relaxed/simple; bh=uokXooPe/YyPpbYpuJUZKqfnA74pZwHjqzOJTRd6cqs=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=GoWWjr1ripXVVv3rg/3p+cZlbLRicUf5WZCSRO/t9S1W5woF5qGevTgldoDYsLBUk+lnqCF0h8VJb2ouYAVZFD6jhcrAxVkMqvH5AQVw3hJN8kGBS04orcStIasgKU38rBKcVzKyZ1ZTW4I4mMUQINAoO9lY8rXt55ztIMwnnPc= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=collabora.com; spf=pass smtp.mailfrom=collabora.com; dkim=pass (2048-bit key) header.d=collabora.com header.i=@collabora.com header.b=ASWRh1wV; arc=none smtp.client-ip=148.251.105.195 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=collabora.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=collabora.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=collabora.com header.i=@collabora.com header.b="ASWRh1wV" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=collabora.com; s=mail; t=1788389655; bh=uokXooPe/YyPpbYpuJUZKqfnA74pZwHjqzOJTRd6cqs=; h=From:Date:Subject:References:In-Reply-To:To:Cc:From; b=ASWRh1wVChyBPbzjq1kQU98yGV59YK+iTLGxXgPnrSmdndmk0Y4g3qc3MkbOxQBbx TloBMyF2XmYbtWwbwV2kArp0F12zEqS6AUhXHT9mDCklZTqEUIlzoQcHa4giyiCCyg PZ5asU8mn5NXwXUP2CnV4QUy93vRc/TeY/iBM/8pNv4w7iZ0c6yimAiG7Kt8X3nE7L ukJvGNQpTZuDmMuqvkBfYtGBZC5FaspIt6WTMU/vFhpt3NFZGddhwMQrMZQgdIIOtw rofjvI9Q2VsstzqfLZtcfB78ol1Y83T5OG1sZw/xLvNs0rLUZGRddUGCPGCs252lUO YO/9b1qyWakvA== Received: from localhost (unknown [100.64.0.241]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange secp256r1 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) (Authenticated sender: cristicc) by bali.collaboradmins.com (Postfix) with ESMTPSA id 46A6917E1122; Thu, 03 Sep 2026 00:54:15 +0200 (CEST) From: Cristian Ciocaltea Date: Thu, 03 Sep 2026 01:54:12 +0300 Subject: [PATCH v4 05/14] drm/rockchip: vop2: Avoid division by zero when computing max_dclk Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: 7bit Message-Id: <20260903-dw-hdmi-qp-yuv-v4-5-fb45bf4147eb@collabora.com> References: <20260903-dw-hdmi-qp-yuv-v4-0-fb45bf4147eb@collabora.com> In-Reply-To: <20260903-dw-hdmi-qp-yuv-v4-0-fb45bf4147eb@collabora.com> To: Sandy Huang , =?utf-8?q?Heiko_St=C3=BCbner?= , Andy Yan , David Airlie , Simona Vetter , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Sascha Hauer , Daniel Stone , Philipp Zabel , Andrzej Hajda , Neil Armstrong , Robert Foss , Laurent Pinchart , Jonas Karlman , Jernej Skrabec , Luca Ceresoli Cc: kernel@collabora.com, Andy Yan , dri-devel@lists.freedesktop.org, linux-rockchip@lists.infradead.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Sashiko , Igor Paunovic X-Mailer: b4 0.15.2 The DCLK reparenting logic in vop2_crtc_atomic_enable() is gated only on the presence of an HDMI PHY PLL on the SoC. This condition is true on any board that wires up an HDMI PHY, even when the CRTC is currently driving a non-HDMI output such as DSI or LVDS. Those encoders do not set vcstate->output_bpc, so it stays 0, hence the subsequent DIV_ROUND_CLOSEST_ULL() then divides by zero. Note this division happens before the drm_for_each_encoder_mask() loop that would establish whether the pipe is actually driven by HDMI, so the loop provides no protection. Default bpc to 8 when it would otherwise be 0. The resulting max_dclk value is a don't-care on the non-HDMI paths that trigger this, since the encoder loop will not select the PHY PLL as the DCLK source there. Fixes: b0362c45c401 ("drm/rockchip: vop2: Check bpc before switching DCLK source") Reported-by: Sashiko Closes: https://lore.kernel.org/all/20260623203310.9F8C81F000E9@smtp.kernel.org/ Link: https://lore.kernel.org/all/20260623203310.9F8C81F000E9@smtp.kernel.org/ Tested-by: Igor Paunovic Signed-off-by: Cristian Ciocaltea --- drivers/gpu/drm/rockchip/rockchip_drm_vop2.c | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/rockchip/rockchip_drm_vop2.c b/drivers/gpu/drm/rockchip/rockchip_drm_vop2.c index 8755b614df34..12a6341e3c98 100644 --- a/drivers/gpu/drm/rockchip/rockchip_drm_vop2.c +++ b/drivers/gpu/drm/rockchip/rockchip_drm_vop2.c @@ -1931,8 +1931,9 @@ static void vop2_crtc_atomic_enable(struct drm_crtc *crtc, * to 4K@60Hz, if available, otherwise keep using the system CRU. */ if (vop2->pll_hdmiphy0 || vop2->pll_hdmiphy1) { - unsigned long max_dclk = DIV_ROUND_CLOSEST_ULL(VOP2_MAX_DCLK_RATE * 8, - vcstate->output_bpc); + unsigned int bpc = vcstate->output_bpc ?: 8; + unsigned long max_dclk = DIV_ROUND_CLOSEST_ULL(VOP2_MAX_DCLK_RATE * 8, bpc); + if (clock <= max_dclk) { drm_for_each_encoder_mask(encoder, crtc->dev, crtc_state->encoder_mask) { struct rockchip_encoder *rkencoder = to_rockchip_encoder(encoder); -- 2.55.0