[PATCH 2/3] dt-bindings: usb: Introduce samsung,snps-dwc3

[Selvarasu Ganesan <selvarasu.g@samsung.com>]

The Samsung Exynos8855 USB glue is not separate from the Synopsys DWC3
core, using a flattened model where the DWC3 controller is directly
addressable rather than nested as a child node of a glue layer.

Describe the Exynos USB block as a single node, referencing the split
out Synopsys DWC3 core properties via snps,dwc3-common.yaml. The new
binding follows the same approach as qcom,snps-dwc3.

A generic fallback compatible "samsung,snps-dwc3" is introduced to
describe this binding, selected by the validator based on the presence
of the fallback string in the compatible list. Future Exynos SoCs
utilizing the same flattened model can be added by extending the
compatible enum with per SoC clock and property constraints.

Co-developed-by: Muhammed Ali <muhammed.ali@samsung.com>
Signed-off-by: Muhammed Ali <muhammed.ali@samsung.com>
Signed-off-by: Selvarasu Ganesan <selvarasu.g@samsung.com>
---

Krzysztof Kozlowski is added as a maintainer of this YAML binding, as
he is the ARM/Samsung SoC architecture maintainer (ARM/SAMSUNG S3C,
S5P AND EXYNOS ARM ARCHITECTURES) who already maintains Samsung Exynos
DT bindings (e.g. samsung,exynos-dwc3.yaml) and reviews all
Samsung related binding changes. This follows the same convention used
by existing Samsung Exynos DT binding schemas.
---
 .../bindings/usb/samsung,snps-dwc3.yaml       | 98 +++++++++++++++++++
 1 file changed, 98 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/usb/samsung,snps-dwc3.yaml

diff --git a/Documentation/devicetree/bindings/usb/samsung,snps-dwc3.yaml b/Documentation/devicetree/bindings/usb/samsung,snps-dwc3.yaml
new file mode 100644
index 000000000000..480308c16f37
--- /dev/null
+++ b/Documentation/devicetree/bindings/usb/samsung,snps-dwc3.yaml
@@ -0,0 +1,98 @@
+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/usb/samsung,snps-dwc3.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Samsung Exynos SoC DWC3 USB Controller
+
+maintainers:
+  - Krzysztof Kozlowski <krzk@kernel.org>
+  - Selvarasu Ganesan <selvarasu.g@samsung.com>
+
+description:
+  Describes the DWC3 USB controller block implemented on Samsung Exynos SoCs.
+
+select:
+  properties:
+    compatible:
+      contains:
+        const: samsung,snps-dwc3
+  required:
+    - compatible
+
+properties:
+  compatible:
+    items:
+      - enum:
+          - samsung,exynos8855-dwc3
+      - const: samsung,snps-dwc3
+
+  reg:
+    maxItems: 1
+
+  power-domains:
+    maxItems: 1
+
+  interrupts:
+    maxItems: 1
+
+  clocks:
+    description: |
+      Several clocks are used, depending on the variant. Typical ones are:
+       - ref: Reference clock for SOF/ITP generation.
+       - bus: Bus (APB) clock for register access.
+    minItems: 1
+    maxItems: 4
+
+  clock-names:
+    minItems: 1
+    maxItems: 4
+
+required:
+  - compatible
+  - reg
+  - clocks
+  - clock-names
+  - interrupts
+
+allOf:
+  - $ref: snps,dwc3-common.yaml#
+
+  - if:
+      properties:
+        compatible:
+          contains:
+            const: samsung,exynos8855-dwc3
+    then:
+      properties:
+        clocks:
+          minItems: 2
+          maxItems: 2
+        clock-names:
+          items:
+            - const: ref
+            - const: bus
+
+unevaluatedProperties: false
+
+examples:
+  - |
+    #include <dt-bindings/interrupt-controller/arm-gic.h>
+
+    usb@13200000 {
+        compatible = "samsung,exynos8855-dwc3",
+                     "samsung,snps-dwc3";
+        reg = <0x13200000 0x10000>;
+        interrupts = <GIC_SPI 436 IRQ_TYPE_LEVEL_HIGH>;
+        clocks = <&usb_clk 0>,
+                 <&usb_clk 1>;
+        clock-names = "ref", "bus";
+        dr_mode = "peripheral";
+        phys = <&usbdrd_phy 0>;
+        phy-names = "usb2-phy";
+        snps,quirk-frame-length-adjustment = <0x20>;
+        snps,dis-u2-freeclk-exists-quirk;
+        snps,gfladj-refclk-lpm-sel-quirk;
+    };
+...
-- 
2.17.1