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a=rsa-sha256; c=relaxed/relaxed; d=mailbox.org; s=mail20150812; t=1788468760; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=kEmfksLg4qJHlSCTmLWtP9kHWyMf/tAclg9vFAXBoXI=; b=YAId4US0O22k7f323jQO/sOtMTPBVUOSk91IGDSpu1ZLb8HmrhU4RhfeH974kDybOSufbU 9kfAe193PRIA5oJnaO/lZk2p3MWWMUHoi02nXICGoXkpNItJTcNcC+0RJER9q+G/zcfyzb 7tRAmgmLklWxbofzYqKwi4MlE+HacYBbivOBEgANfUxhzIIrGZdVSzVyTM7JK9L9T8cjO3 LDL7UDORXFclkbfS+YlglXULW0sJ/XYKNqHox1NLd3MjyMy49pCmWB7lz5Wk18WI0VHrUZ ySXUVhy/gQukElF5LiI2BDyVVBeGhYNEauwuxiTs142WDUB5vAnT0KRbjyouWA== To: linux-pci@vger.kernel.org Cc: Marek Vasut , =?UTF-8?q?Krzysztof=20Wilczy=C5=84ski?= , Bjorn Helgaas , Conor Dooley , Geert Uytterhoeven , Koichiro Den , Krzysztof Kozlowski , Lorenzo Pieralisi , Magnus Damm , Manivannan Sadhasivam , Rob Herring , Yoshihiro Shimoda , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-renesas-soc@vger.kernel.org Subject: [PATCH 6/6] arm64: dts: renesas: r8a779h0: Add PCIe Application/Local register reset Date: Thu, 3 Sep 2026 22:50:57 +0200 Message-ID: <20260903205153.283553-6-marek.vasut+renesas@mailbox.org> In-Reply-To: <20260903205153.283553-1-marek.vasut+renesas@mailbox.org> References: <20260903205153.283553-1-marek.vasut+renesas@mailbox.org> Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit X-MBO-RS-META: gu1dkp5cbhpqcb571ayordeesxnptdpx X-MBO-RS-ID: 9ab699da2505a2ba699 X-Rspamd-Queue-Id: 4hbWy22bXCzMlG4 Renesas R-Car V4M documentation R19UH0217EJ0110 Rev.1.10 , Jun. 30, 2026 attachment R-CarV4M_UM_009_SRCRn_FSRCHKRAn_FSRCHKRBn_r1p10.xlsx row 411 describes PCIEC ch0 Application/Local register reset. Add the reset into both RC and EP DT nodes of PCIe controller. Signed-off-by: Marek Vasut --- Cc: "Krzysztof Wilczyński" Cc: Bjorn Helgaas Cc: Conor Dooley Cc: Geert Uytterhoeven Cc: Koichiro Den Cc: Krzysztof Kozlowski Cc: Lorenzo Pieralisi Cc: Magnus Damm Cc: Manivannan Sadhasivam Cc: Rob Herring Cc: Yoshihiro Shimoda Cc: devicetree@vger.kernel.org Cc: linux-kernel@vger.kernel.org Cc: linux-pci@vger.kernel.org Cc: linux-renesas-soc@vger.kernel.org --- arch/arm64/boot/dts/renesas/r8a779h0.dtsi | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/arch/arm64/boot/dts/renesas/r8a779h0.dtsi b/arch/arm64/boot/dts/renesas/r8a779h0.dtsi index aca6ffc68c30a..c66fb22d72aa8 100644 --- a/arch/arm64/boot/dts/renesas/r8a779h0.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a779h0.dtsi @@ -688,8 +688,8 @@ pciec0: pcie@e65d0000 { clocks = <&cpg CPG_MOD 624>, <&pcie0_clkref>; clock-names = "core", "ref"; power-domains = <&sysc R8A779H0_PD_A2PCIPHY>; - resets = <&cpg 624>; - reset-names = "pwr"; + resets = <&cpg 624>, <&cpg 1121>; + reset-names = "pwr", "core"; max-link-speed = <4>; num-lanes = <2>; #address-cells = <3>; @@ -724,8 +724,8 @@ pciec0_ep: pcie-ep@e65d0000 { clocks = <&cpg CPG_MOD 624>, <&pcie0_clkref>; clock-names = "core", "ref"; power-domains = <&sysc R8A779H0_PD_A2PCIPHY>; - resets = <&cpg 624>; - reset-names = "pwr"; + resets = <&cpg 624>, <&cpg 1121>; + reset-names = "pwr", "core"; max-link-speed = <4>; num-lanes = <2>; max-functions = /bits/ 8 <2>; -- 2.53.0