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[2001:4c4e:1b87:1500:cb6e:f488:a18f:9c42]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-49ce554d52esm135575435e9.3.2026.09.04.06.09.23 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 04 Sep 2026 06:09:25 -0700 (PDT) From: Igor Paunovic To: Tomeu Vizoso , Oded Gabbay , Heiko Stuebner Cc: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Sidong Yang , Diederik de Haas , Sebastian Reichel , Jiaxing Hu , Nicolas Dufresne , Jonas Karlman , dri-devel@lists.freedesktop.org, linux-rockchip@lists.infradead.org, linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Igor Paunovic Subject: [PATCH 2/7] dt-bindings: npu: rockchip: allow DVFS and thermal properties Date: Fri, 4 Sep 2026 15:08:53 +0200 Message-ID: <20260904130858.27803-3-royalnet026@gmail.com> X-Mailer: git-send-email 2.53.0 In-Reply-To: <20260904130858.27803-1-royalnet026@gmail.com> References: <20260904130858.27803-1-royalnet026@gmail.com> Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit The three NPU cores on the RK3588 are fed by a single clock and a single supply, and the firmware accepts a fixed set of rates for that clock. Describing those rates as an operating-points-v2 table is what lets a driver scale the NPU instead of leaving it at whatever rate the bootloader set, so allow the property on the core node. Throttling the NPU from a thermal zone needs the same node to be usable as a cooling device, so allow #cooling-cells too. Both properties belong on the core that carries the shared clock, not on all three: the cores have no clock of their own and cannot be scaled or throttled independently. Naming one representative node for a shared frequency domain is the established shape, as in "Cpufreq cooling device on CPU0" in Documentation/devicetree/bindings/thermal/thermal-cooling-devices.yaml. The schema cannot enforce that placement, because all three cores share a compatible string and a node name pattern, so which core carries them stays a devicetree convention. That is the same situation as for CPU cooling, where cpus.yaml does not restrict #cooling-cells to cpu@0 either. The example gains #cooling-cells; the operating-points-v2 property is exercised by the RK3588 devicetree later in this series. Signed-off-by: Igor Paunovic Assisted-by: LLM checkpatch dt_binding_check --- .../bindings/npu/rockchip,rk3588-rknn-core.yaml | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/Documentation/devicetree/bindings/npu/rockchip,rk3588-rknn-core.yaml b/Documentation/devicetree/bindings/npu/rockchip,rk3588-rknn-core.yaml index caca2a4903cd1..595aacfbf8608 100644 --- a/Documentation/devicetree/bindings/npu/rockchip,rk3588-rknn-core.yaml +++ b/Documentation/devicetree/bindings/npu/rockchip,rk3588-rknn-core.yaml @@ -42,6 +42,13 @@ properties: - const: npu - const: pclk + "#cooling-cells": + description: + Present on the core that drives the shared NPU clock, which is the one + the operating-points-v2 table below is attached to. The other cores + cannot be throttled independently of it. + const: 2 + interrupts: maxItems: 1 @@ -50,6 +57,8 @@ properties: npu-supply: true + operating-points-v2: true + power-domains: maxItems: 1 @@ -100,6 +109,7 @@ examples: clocks = <&cru ACLK_NPU0>, <&cru HCLK_NPU0>, <&scmi_clk SCMI_CLK_NPU>, <&cru PCLK_NPU_ROOT>; clock-names = "aclk", "hclk", "npu", "pclk"; + #cooling-cells = <2>; interrupts = ; iommus = <&rknn_mmu_0>; npu-supply = <&vdd_npu_s0>; -- 2.43.0