Re: [PATCH net-next v9 3/4] net: dsa: microchip: Support Microchip KSZ8995XA / KS8995XA

[sashiko-bot@kernel.org]

Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider:
- [Medium] Missing polling loop or delay after triggering self-clearing PHY soft reset.
--

commit 702792aed3ea3d1bc269d8039fc614882297cc87
Author: Linus Walleij <linusw@kernel.org>

net: dsa: microchip: Support Microchip KSZ8995XA / KS8995XA

This patch adds support for the Microchip KSZ8995XA switch to the KSZ
driver, handling its specific port configurations, priority levels, and
packet-size semantics.

> diff --git a/drivers/net/dsa/microchip/ksz8.c b/drivers/net/dsa/microchip/ksz8.c
> --- a/drivers/net/dsa/microchip/ksz8.c
> +++ b/drivers/net/dsa/microchip/ksz8.c

[ ... ]

> @@ -253,7 +254,17 @@ static int ksz8463_reset_switch(struct ksz_device *dev)
>  
>  static int ksz8_reset_switch(struct ksz_device *dev)
>  {
> -	if (ksz_is_ksz88x3(dev)) {
> +	if (ksz_is_ksz8995xa(dev)) {
> +		unsigned int port;
> +
> +		/* The KSZ8995XA switch itself cannot be reset by software, but
> +		 * often boot loaders have fun with ports, so reset them. This
> +		 * reset bit is self-clearing.
> +		 */
> +		for (port = 0; port < dev->info->port_cnt; port++)
> +			ksz_port_cfg(dev, port, REG_PORT_STATUS_3,
> +				     PORT_PHY_SOFT_RESET, true);

[Severity: Medium]
Is a delay or polling loop needed here after asserting the self-clearing
reset bit?

If the PHY requires time to complete its soft reset, subsequent register
configurations performed by ksz8_setup() immediately after returning from
ksz8_reset_switch() might be ignored or cause hardware state issues.

> +	} else if (ksz_is_ksz88x3(dev)) {
>  		/* reset switch */

[ ... ]

-- 
Sashiko AI review · https://sashiko.dev/#/patchset/20260906-ks8995-to-ksz8-v9-0-8d8815a91bd8@kernel.org?part=3