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[92.247.61.126]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-48594172546sm26855073f8f.15.2026.09.08.04.10.20 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 08 Sep 2026 04:10:20 -0700 (PDT) From: Petko Manolov To: linux-kernel@vger.kernel.org Cc: devicetree@vger.kernel.org, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, dinguyen@kernel.org, Petko Manolov Subject: [PATCH v2 1/1] ARM: dts: draeger: Add socfpga devicetree for Draeger's M48 board. Date: Tue, 8 Sep 2026 14:10:00 +0300 Message-ID: <20260908111011.960876-2-petko.manolov@konsulko.com> X-Mailer: git-send-email 2.47.3 In-Reply-To: <20260908111011.960876-1-petko.manolov@konsulko.com> References: <20260908111011.960876-1-petko.manolov@konsulko.com> Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Signed-off-by: Petko Manolov --- .../devicetree/bindings/arm/altera.yaml | 1 + arch/arm/boot/dts/intel/socfpga/Makefile | 1 + .../socfpga/socfpga_cyclone5_draeger_m48.dts | 130 ++++++++++++++++++ 3 files changed, 132 insertions(+) create mode 100644 arch/arm/boot/dts/intel/socfpga/socfpga_cyclone5_draeger_m48.dts diff --git a/Documentation/devicetree/bindings/arm/altera.yaml b/Documentation/devicetree/bindings/arm/altera.yaml index 3030cf46fe74..8ed1ba733510 100644 --- a/Documentation/devicetree/bindings/arm/altera.yaml +++ b/Documentation/devicetree/bindings/arm/altera.yaml @@ -47,6 +47,7 @@ properties: - enum: - altr,socfpga-cyclone5-socdk - denx,mcvevk + - draeger,M48 - ebv,socrates - macnica,sodia - novtech,chameleon96 diff --git a/arch/arm/boot/dts/intel/socfpga/Makefile b/arch/arm/boot/dts/intel/socfpga/Makefile index 8df0976da01c..cdcea11abdfa 100644 --- a/arch/arm/boot/dts/intel/socfpga/Makefile +++ b/arch/arm/boot/dts/intel/socfpga/Makefile @@ -11,6 +11,7 @@ dtb-$(CONFIG_ARCH_INTEL_SOCFPGA) += \ socfpga_arria10_mercury_aa1_st1_emmc.dtb \ socfpga_arria10_mercury_aa1_st1_qspi.dtb \ socfpga_arria10_mercury_aa1_st1_sdmmc.dtb \ + socfpga_cyclone5_draeger_m48.dtb \ socfpga_cyclone5_mercury_sa1_pe1_emmc.dtb \ socfpga_cyclone5_mercury_sa1_pe1_qspi.dtb \ socfpga_cyclone5_mercury_sa1_pe1_sdmmc.dtb \ diff --git a/arch/arm/boot/dts/intel/socfpga/socfpga_cyclone5_draeger_m48.dts b/arch/arm/boot/dts/intel/socfpga/socfpga_cyclone5_draeger_m48.dts new file mode 100644 index 000000000000..423c76cd1d4a --- /dev/null +++ b/arch/arm/boot/dts/intel/socfpga/socfpga_cyclone5_draeger_m48.dts @@ -0,0 +1,130 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * (C) Copyright 2020 Draeger and Licensors, info@draeger.com + */ +#include "socfpga_cyclone5.dtsi" + +/ { + model = "Draeger M48 Cyclone V SoC"; + compatible = "draeger,M48", "altr,socfpga-cyclone5", "altr,socfpga"; + + chosen { + bootargs = "earlyprintk"; + stdout-path = "serial0:115200n8"; + }; + + memory@0 { + name = "memory"; + device_type = "memory"; + reg = <0x0 0x40000000>; + + /* 1GB */ + }; + + aliases { + /* this allow the ethaddr uboot environmnet variable contents + * to be added to the gmac0 device tree blob. + */ + ethernet0 = &gmac0; + }; + + soc { + gpio3: gpio@ff202000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "snps,dw-apb-gpio"; + reg = <0xff202000 0x20>; + status = "okay"; + + portd: gpio-controller@0 { + compatible = "snps,dw-apb-gpio-port"; + gpio-controller; + #gpio-cells = <2>; + snps,nr-gpios = <2>; + reg = <0>; + bank-name = "SYNC_I"; + }; + }; + + gpio4: gpio@ff202020 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "snps,dw-apb-gpio"; + reg = <0xff202020 0x20>; + status = "okay"; + + porte: gpio-controller@0 { + compatible = "snps,dw-apb-gpio-port"; + gpio-controller; + #gpio-cells = <2>; + snps,nr-gpios = <2>; + reg = <0>; + bank-name = "SYNC_O"; + }; + }; + }; +}; + +&gmac0 { + status = "okay"; + phy-mode = "rgmii-id"; + rxc-skew-ps = <1860>; + rxd0-skew-ps = <0>; + rxd1-skew-ps = <0>; + rxd2-skew-ps = <0>; + rxd3-skew-ps = <0>; + rxdv-skew-ps = <0>; + txc-skew-ps = <900>; + txd0-skew-ps = <0>; + txd1-skew-ps = <0>; + txd2-skew-ps = <0>; + txd3-skew-ps = <0>; + txen-skew-ps = <0>; +}; + +&gpio0 { + status = "okay"; +}; + +&gpio1 { + status = "okay"; +}; + +&gpio2 { + status = "okay"; +}; + +&i2c0 { + status = "okay"; + clock-frequency = <100000>; + + eeprom_mac: eeprom@50 { + compatible = "atmel,24c08"; + reg = <0x50>; + pagesize = <16>; + }; +}; + +&mmc0 { + status = "okay"; +}; + +&qspi { + status = "okay"; + + flash: flash@0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "micron,n25q256a", "jedec,spi-nor"; + reg = <0>; + + /* chip select */ + spi-max-frequency = <100000000>; + m25p,fast-read; + cdns,read-delay = <4>; + cdns,tshsl-ns = <50>; + cdns,tsd2d-ns = <50>; + cdns,tchsh-ns = <4>; + cdns,tslch-ns = <4>; + }; +}; -- 2.47.3