[PATCH 1/4] dt-bindings: ufs: Add nvidia,tegra264-ufs

[Kartik Rajput <kkartik@nvidia.com>]

Add binding for the UFS host controller on NVIDIA Tegra264 SoCs. The
controller supports UFS 3.1 up to HS-G4B on two data lanes.

Signed-off-by: Kartik Rajput <kkartik@nvidia.com>
---
 .../bindings/ufs/nvidia,tegra264-ufs.yaml          | 124 +++++++++++++++++++++
 1 file changed, 124 insertions(+)

diff --git a/Documentation/devicetree/bindings/ufs/nvidia,tegra264-ufs.yaml b/Documentation/devicetree/bindings/ufs/nvidia,tegra264-ufs.yaml
new file mode 100644
index 000000000000..5a9837cb43dd
--- /dev/null
+++ b/Documentation/devicetree/bindings/ufs/nvidia,tegra264-ufs.yaml
@@ -0,0 +1,124 @@
+# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/ufs/nvidia,tegra264-ufs.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: NVIDIA Tegra264 UFS Host Controller
+
+maintainers:
+  - Kartik Rajput <kkartik@nvidia.com>
+  - Thierry Reding <treding@nvidia.com>
+
+properties:
+  compatible:
+    const: nvidia,tegra264-ufs
+
+  reg:
+    items:
+      - description: UFS Host Controller registers
+      - description: UFS auxiliary registers
+
+  reg-names:
+    items:
+      - const: ufs
+      - const: aux
+
+  clocks:
+    items:
+      - description: UFS host controller functional clock
+      - description: UFS host controller divider clock
+      - description: UFS reference clock (PLLREFUFS output)
+      - description: UFS device-side reference clock
+      - description: M-PHY reference clock (UPHY0 PLL4 digital output)
+
+  clock-names:
+    items:
+      - const: ufs
+      - const: div
+      - const: ref
+      - const: ref-dev
+      - const: phy
+
+  resets:
+    items:
+      - description: UFS host controller reset
+      - description: UFS host controller AXI-master reset
+      - description: UFS host controller low-power sequencer reset
+
+  reset-names:
+    items:
+      - const: ufs
+      - const: axi
+      - const: lp
+
+  phys:
+    items:
+      - description: M-PHY lane 0 transmit
+      - description: M-PHY lane 0 receive
+      - description: M-PHY lane 1 transmit
+      - description: M-PHY lane 1 receive
+
+  phy-names:
+    items:
+      - const: mphy-l0-tx
+      - const: mphy-l0-rx
+      - const: mphy-l1-tx
+      - const: mphy-l1-rx
+
+  iommus:
+    maxItems: 1
+
+  dma-coherent: true
+
+required:
+  - compatible
+  - reg
+  - reg-names
+  - clocks
+  - clock-names
+  - resets
+  - reset-names
+  - phys
+  - phy-names
+  - iommus
+  - dma-coherent
+
+allOf:
+  - $ref: ufs-common.yaml
+
+unevaluatedProperties: false
+
+examples:
+  - |
+    #include <dt-bindings/clock/nvidia,tegra264.h>
+    #include <dt-bindings/interrupt-controller/arm-gic.h>
+    #include <dt-bindings/phy/nvidia,tegra264-mphy.h>
+    #include <dt-bindings/reset/nvidia,tegra264.h>
+
+    ufs@b8d0000 {
+        compatible = "nvidia,tegra264-ufs";
+        reg = <0xb8d0000 0x10000>,
+              <0xb8e0000 0x8000>;
+        reg-names = "ufs", "aux";
+        interrupts = <GIC_SPI 951 IRQ_TYPE_LEVEL_HIGH>;
+        clocks = <&bpmp TEGRA264_CLK_UFSHC_CG_SYS>,
+                 <&bpmp TEGRA264_CLK_UFSHC_CG_SYS_DIV>,
+                 <&bpmp TEGRA264_CLK_PLLREFUFS_CLKOUT624>,
+                 <&bpmp TEGRA264_CLK_PLLREFUFS_UFSDEV_REFCLKOUT>,
+                 <&bpmp TEGRA264_CLK_UPHY0_PLL4_XDIG>;
+        clock-names = "ufs", "div", "ref", "ref-dev", "phy";
+        resets = <&bpmp TEGRA264_RESET_UFSHC>,
+                 <&bpmp TEGRA264_RESET_UFSHC_AXI_M>,
+                 <&bpmp TEGRA264_RESET_UFSHC_LP_SEQ>;
+        reset-names = "ufs", "axi", "lp";
+        phys = <&mphy TEGRA_MPHY_L0_TX>,
+               <&mphy TEGRA_MPHY_L0_RX>,
+               <&mphy TEGRA_MPHY_L1_TX>,
+               <&mphy TEGRA_MPHY_L1_RX>;
+        phy-names = "mphy-l0-tx", "mphy-l0-rx",
+                    "mphy-l1-tx", "mphy-l1-rx";
+        iommus = <&smmu 0x20>;
+        dma-coherent;
+    };
+...

-- 
2.43.0