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Wed, 9 Sep 2026 06:05:15 +0000 X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 222.71.101.198) smtp.mailfrom=cixtech.com; dkim=none (message not signed) header.d=none;dmarc=bestguesspass action=none header.from=cixtech.com; Received-SPF: Pass (protection.outlook.com: domain of cixtech.com designates 222.71.101.198 as permitted sender) receiver=protection.outlook.com; client-ip=222.71.101.198; helo=smtprelay.cixcomputing.com; pr=C Received: from smtprelay.cixcomputing.com (222.71.101.198) by TY2PEPF0000AB8A.mail.protection.outlook.com (10.167.253.8) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.21.406.5 via Frontend Transport; Wed, 9 Sep 2026 06:05:15 +0000 Received: from ubuntu (unknown [172.20.64.99]) by smtprelay.cixcomputing.com (Postfix) with ESMTPSA id 6A3164092106; Wed, 9 Sep 2026 14:05:13 +0800 (CST) From: Jelly Jia To: Conor Dooley Cc: Jelly Jia , vkoul@kernel.org, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, devicetree@vger.kernel.org, Frank.Li@kernel.org, robin.murphy@arm.com, cix-kernel-upstream@cixtech.com, dmaengine@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Subject: Re: [PATCH v1 3/5] dt-bindings: dma: Add CIX Sky1 DMA-350 integration Date: Wed, 9 Sep 2026 14:05:12 +0800 Message-ID: <20260909060512.3524983-1-Jelly.Jia@cixtech.com> X-Mailer: git-send-email 2.55.0 In-Reply-To: <20260907-retorted-unfasten-e985a6d4f26f@spud> References: <20260907-retorted-unfasten-e985a6d4f26f@spud> Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: TY2PEPF0000AB8A:EE_|JH0PR06MB7210:EE_ Content-Type: text/plain X-MS-Office365-Filtering-Correlation-Id: a6635ce2-b2ae-4fd8-0970-08df0e385135 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|7416014|82310400026|23010399003|36860700016|1800799024|376014|10067099003|6133799003|22082099003|18002099003|56012099006; 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X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: zyfKv1pOSHvc2gtgGoRVMxqliWNKgLccJ4IQLKULLgm0686KftQ9bcmLztgwNcKoVh07KWdmCvskN8axrL4i+HDtfgx1f1I6GWwOCelEL61zoFCcEWxVSWKn7KYXn5BIRwV7pAfVT9SNya2JJeQj2bIK4jqLa1i7hkNMyRsrDJsjseKrHo+x8VgueyCNkBXFROdl/7SB1VVpDi/rkGTDT7v+Jgh4w5MzZrfQR+mp0hKcJOK4yzoa/lM5EzsTaP6XQxIagXl6QBo/DyDvaDNFYlfBXgJ36xoZK93lQ9nkK7+YTGbt/XbRRoI5yYnJcW2VuyqCR9CnQMXINbORqQRO0RpTdW1rzgdRb0aYlG/xZ13a+jZ8V5mPoRF/BiBiD+8vGFyeTaiEUqACH/mPk2xT6RQLqZ9cMizc8TBRRUZVgFLGjZZe7IkE4e3xU6W2uWEu X-OriginatorOrg: cixtech.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 09 Sep 2026 06:05:15.0712 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: a6635ce2-b2ae-4fd8-0970-08df0e385135 X-MS-Exchange-CrossTenant-Id: 0409f77a-e53d-4d23-943e-ccade7cb4811 X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=0409f77a-e53d-4d23-943e-ccade7cb4811;Ip=[222.71.101.198];Helo=[smtprelay.cixcomputing.com] X-MS-Exchange-CrossTenant-AuthSource: TY2PEPF0000AB8A.apcprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: JH0PR06MB7210 Hi Conor, Thanks for the review. > I cannot really speak to whether this is a correct thing to do with a > dma-350, but it seems to me like something that should be resolved with > a device specific comaptible in the dma-350 node. Someone more familar > with the IP will have to comment on that. The wrapper is there to keep the platform integration bits (clocks, resets, interrupt routing) out of the generic driver: the arm-dma-350 child stays plain so the existing driver binds to it unchanged. I don't know whether other dma350 integrations need the same resources, so I did not want to push them into the generic node. > However I would like to know how this impacts the existing dma-350 in he > sky1 devicetree. Patch 5 converts the existing FCH node to this form: the register window and the eight GIC interrupts are unchanged, the arm-dma-350 controller becomes the dma-controller@0 child, and the SCMI clock feeding the instance is added. The AUDSS instance is new. I'll describe this conversion in the patch 5 commit message in v2. Best regards, Jelly