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They are described individually as nvmem cells. Signed-off-by: Simeon Marijon Signed-off-by: Patrice Chotard --- arch/arm/boot/dts/st/stm32mp151.dtsi | 82 ++++++++++++++++++++++++++++++++++++ 1 file changed, 82 insertions(+) diff --git a/arch/arm/boot/dts/st/stm32mp151.dtsi b/arch/arm/boot/dts/st/stm32mp151.dtsi index 84f68e8563d8..0ad75e010839 100644 --- a/arch/arm/boot/dts/st/stm32mp151.dtsi +++ b/arch/arm/boot/dts/st/stm32mp151.dtsi @@ -2060,7 +2060,89 @@ i2c6: i2c@5c009000 { tamp: tamp@5c00a000 { compatible = "st,stm32-tamp", "syscon", "simple-mfd"; + #address-cells = <1>; + #size-cells = <1>; reg = <0x5c00a000 0x400>; + ranges; + + nvram: nvram@5c00a100 { + compatible = "st,stm32mp15-tamp-nvram"; + reg = <0x5c00a100 0x80>; + + nvmem-layout { + compatible = "fixed-layout"; + #address-cells = <1>; + #size-cells = <1>; + wakeup_sec: tamp-bkp@0 { + reg = <0x0 0x4>; + }; + + m4_security_perimeter_exti1: tamp-bkp@4 { + /* see cortex-m4 wake up feature */ + reg = <0x4 0x4>; + }; + + m4_security_perimeter_exti2: tamp-bkp@8 { + /* see cortex-m4 wake up feature */ + reg = <0x8 0x4>; + }; + + m4_security_perimeter_exti3: tamp-bkp@c { + /* see cortex-m4 wtake up feature */ + reg = <0xc 0x4>; + }; + + magic_number: tamp-bkp@10 { + /* see ddr and cpu wake up management feature */ + reg = <0x10 0x4>; + }; + + branch_address: tamp-bkp@14 { + /* see ddr and cpu wake up management feature */ + reg = <0x14 0x4>; + }; + + fwu_info: tamp-bkp@28 { + /* see firmware update info feature */ + reg = <0x28 0x4>; + }; + + copro_rsc_tbl_address: tamp-bkp@44 { + /* see cortex-m4 management feature */ + reg = <0x44 0x4>; + }; + + cortex_m_state: tamp-bkp@48 { + /* see cortex-m4 management feature */ + reg = <0x48 0x4>; + }; + + boot_mode: tamp-bkp@50 { + /* see boot mode selection feature */ + reg = <0x50 0x4>; + }; + + boot_counter: tamp-bkp@54 { + /* see boot counter feature */ + reg = <0x54 0x4>; + }; + + m4_wakeup_area_start: tamp-bkp@58 { + /* see cortex-m4 wake up feature */ + reg = <0x58 0x4>; + }; + + m4_wakeup_area_length: tamp-bkp@5c { + /* see cortex-m4 wake up feature */ + reg = <0x5c 0x4>; + }; + + m4_wakeup_area_hash: tamp-bkp@60 { + /* SHA-0x100 value see Cortex-M4 wake up feature */ + reg = <0x60 0x20>; + }; + }; + }; }; /* -- 2.43.0