From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from Atcsqr.andestech.com (atcsqr.andestech.com [220.128.198.184]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 78FE1450415; Fri, 11 Sep 2026 07:42:22 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=220.128.198.184 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1789112547; cv=none; b=PtOBF6J8GKdmNHgWWdvzBYb+LK94bIM4Q8xJr8LvQ3YdhoQkzcTjN15zbE2nHGG5A2oxecYtfOVvbfP3A25Qit9xJhoFtjTqh8vZxlBEakWDbpeRS0ETF7y2FEbW6Wlgcy0zqYcuX6F+FC4+0jCqFCrkzM311q8HNmfIXw4DsfE= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1789112547; c=relaxed/simple; bh=BMkgbPKviKHC4rd29McGJoIAKL4ZtGWMSuVQcHUw27I=; h=From:To:CC:Subject:Date:Message-ID:MIME-Version:Content-Type; b=X9EKQh/c+soYs3ejAms/J7JW08ogfF9cyEoev41aTmVfqB1vkWoXbEAQXFm5BUrwJfsogffXd80I8+8e781Huk3+IlgFpErPeNrY8gKBIEhY5vfi+XGMLeWvxeigEMT2WtKKu2ztAFau4TdRLgbBDlLk3zC5IkE9/+32GAVwCII= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=andestech.com; spf=pass smtp.mailfrom=andestech.com; arc=none smtp.client-ip=220.128.198.184 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=andestech.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=andestech.com Received: from Atcsqr.andestech.com (localhost [127.0.0.2] (may be forged)) by Atcsqr.andestech.com with ESMTP id 68B7PxDH008840; Fri, 11 Sep 2026 15:25:59 +0800 (+08) (envelope-from cl634@andestech.com) Received: from mail.andestech.com (atcpcs53.andestech.com [10.0.1.153]) by Atcsqr.andestech.com with ESMTPS id 68B7PY1v008516 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=OK); Fri, 11 Sep 2026 15:25:34 +0800 (+08) (envelope-from cl634@andestech.com) Received: from ATCPCS34.andestech.com (10.0.1.134) by atcpcs53.andestech.com (10.0.1.153) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.2.2562.43; Fri, 11 Sep 2026 15:25:34 +0800 Received: from swlinux02.andestech.com (10.0.15.183) by ATCPCS34.andestech.com (10.0.1.134) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.39; Fri, 11 Sep 2026 15:25:33 +0800 From: CL Wang To: Vinod Koul , Rob Herring , "Krzysztof Kozlowski" , Conor Dooley CC: Frank Li , Kees Cook , "Gustavo A . R . Silva" , , , , , , Subject: [PATCH v6 0/2] dmaengine: atcdmac300: Add Andes ATCDMAC300 DMA driver Date: Fri, 11 Sep 2026 15:25:22 +0800 Message-ID: <20260911072524.1297406-1-cl634@andestech.com> X-Mailer: git-send-email 2.34.1 Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-ClientProxiedBy: ATCPCS33.andestech.com (10.0.1.100) To ATCPCS34.andestech.com (10.0.1.134) X-DKIM-Results: atcpcs53.andestech.com; dkim=none; X-DNSRBL: X-SPAM-SOURCE-CHECK: pass X-MAIL:Atcsqr.andestech.com 68B7PxDH008840 This patch series adds support for the Andes ATCDMAC300 DMA controller, a memory-to-memory and peripheral DMA controller that provides scatter-gather, cyclic, and slave transfer capabilities. The ATCDMAC300 IP is embedded in AndesCore-based platforms or SoCs such as AE350 and Qilai. Changes in v6: - Rebase onto dmaengine/next; no functional changes from v5 - Fold the MAINTAINERS entry into the driver patch instead of carrying it as a separate patch (series is now 2 patches) Changes in v5: - Update copyright year to 2026 - Remove redundant headers (init.h, iopoll.h, mod_devicetable.h) - Move atcdmac_init_iocp() before of_dma_controller_register() in probe - Change builtin_platform_driver() to module_platform_driver() - Implement .remove callback to support safe module unloading - Update Kconfig entry from bool to tristate - Add MODULE_AUTHOR, MODULE_DESCRIPTION, MODULE_LICENSE macros Changes in v4: - Use items list format with descriptions for reg property in DT binding as suggested by Conor Dooley - Re-add Acked-by from Conor Dooley for DT binding patch Changes in v3: - Rename DT binding file from andestech,qilai-dma.yaml to andestech,ae350-dma.yaml - Deprecate IP-core-based compatible usage and align with SoC/platform-based strings - Dropped Acked-by from Conor Dooley due to the above binding change - Remove "andestech,atcdmac300" from of_device_id table - Replace deprecated tasklet with threaded IRQ using devm_request_threaded_irq() and IRQF_ONESHOT - Update locking from spin_lock_bh() to spin_lock_irqsave() - Use builtin_platform_driver() instead of module_platform_driver() - Remove "select DMATEST" from Kconfig - Add separate MAINTAINERS patch (patch 3/3) Please kindly review. CL Wang (2): dt-bindings: dmaengine: Add support for ATCDMAC300 DMA engine dmaengine: atcdmac300: Add driver for Andes ATCDMAC300 DMA controller .../bindings/dma/andestech,ae350-dma.yaml | 67 + MAINTAINERS | 6 + drivers/dma/Kconfig | 11 + drivers/dma/Makefile | 1 + drivers/dma/atcdmac300.c | 1518 +++++++++++++++++ drivers/dma/atcdmac300.h | 296 ++++ 6 files changed, 1899 insertions(+) create mode 100644 Documentation/devicetree/bindings/dma/andestech,ae350-dma.yaml create mode 100644 drivers/dma/atcdmac300.c create mode 100644 drivers/dma/atcdmac300.h -- 2.34.1