From: Changhuang Liang <changhuang.liang@starfivetech.com>
To: hal.feng@starfivetech.com
Cc: aou@eecs.berkeley.edu, conor@kernel.org,
devicetree@vger.kernel.org, emil.renner.berthing@canonical.com,
krzk+dt@kernel.org, linux-kernel@vger.kernel.org,
linux-pwm@vger.kernel.org, linux-riscv@lists.infradead.org,
p.zabel@pengutronix.de, palmer@dabbelt.com, pjw@kernel.org,
robh@kernel.org, ukleinek@kernel.org,
changhuang.liang@starfivetech.com
Subject: [RESEND v22 1/3] dt-bindings: pwm: opencores: Update compatibles, examples and maintainers
Date: Fri, 11 Sep 2026 03:16:05 -0700 [thread overview]
Message-ID: <20260911101605.146710-1-changhuang.liang@starfivetech.com> (raw)
In-Reply-To: <20260810030714.48100-2-hal.feng@starfivetech.com>
Hello Conor,
Sorry to bother you. I discussed it with Hal, and I will pick up this series
later to add PWM support for JHB100.
> Remove the jh8100 compatible since the JH8100 SoC has been canceled and
> will not be released. Add the jhb100 compatible to replace it.
>
> Change the register size in examples to 0x10, since an OpenCores PTC IP
> has only 4 32-bit registers: CNTR, HRC, LRC and CTRL.
>
> I will maintain this pwm module in place of William.
>
> Acked-by: Conor Dooley <conor.dooley@microchip.com>
> Fixes: 2529085831b0 ("dt-bindings: pwm: Add bindings for OpenCores PWM Controller")
> Signed-off-by: Hal Feng <hal.feng@starfivetech.com>
> ---
> Documentation/devicetree/bindings/pwm/opencores,pwm.yaml | 6 +++---
> 1 file changed, 3 insertions(+), 3 deletions(-)
>
> diff --git a/Documentation/devicetree/bindings/pwm/opencores,pwm.yaml b/Documentation/devicetree/bindings/pwm/opencores,pwm.yaml
> index 52a59d245cdb..42c5d2b6326d 100644
> --- a/Documentation/devicetree/bindings/pwm/opencores,pwm.yaml
> +++ b/Documentation/devicetree/bindings/pwm/opencores,pwm.yaml
> @@ -7,7 +7,7 @@ $schema: http://devicetree.org/meta-schemas/core.yaml#
> title: OpenCores PWM controller
>
> maintainers:
> - - William Qiu <william.qiu@starfivetech.com>
> + - Hal Feng <hal.feng@starfivetech.com>
>
> description:
> The OpenCores PTC ip core contains a PWM controller. When operating in PWM
> @@ -23,7 +23,7 @@ properties:
> - enum:
> - starfive,jh7100-pwm
> - starfive,jh7110-pwm
> - - starfive,jh8100-pwm
> + - starfive,jhb100-pwm
> - const: opencores,pwm-v1
>
Compared with the JH7110 PWM, the JHB100 PWM has been modified. The JH7110 PWM
is inverted polarity by default, which is consistent with the design of
opencores,pwm-v1, but the JHB100 PWM has been modified to normal polarity,
so it no longer conforms to the design of opencores,pwm-v1. Therefore, I plan
to revise the binding here again:
properties:
compatible:
oneOf:
- items:
- enum:
- starfive,jh7100-pwm
- starfive,jh7110-pwm
- const: opencores,pwm-v1
- const: starfive,jhb100-pwm
Do you think this makes sense?
> reg:
> @@ -49,7 +49,7 @@ examples:
> - |
> pwm@12490000 {
> compatible = "starfive,jh7110-pwm", "opencores,pwm-v1";
> - reg = <0x12490000 0x10000>;
> + reg = <0x12490000 0x10>;
> clocks = <&clkgen 181>;
> resets = <&rstgen 109>;
> #pwm-cells = <3>;
> --
Best Regards,
Changhuang
next prev parent reply other threads:[~2026-09-11 10:16 UTC|newest]
Thread overview: 7+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-08-10 3:07 [RESEND v22 0/3] Add OpenCores PTC PWM support Hal Feng
2026-08-10 3:07 ` [RESEND v22 1/3] dt-bindings: pwm: opencores: Update compatibles, examples and maintainers Hal Feng
2026-09-11 10:16 ` Changhuang Liang [this message]
2026-08-10 3:07 ` [RESEND v22 2/3] riscv: dts: starfive: Correct pwm nodes Hal Feng
2026-08-10 3:07 ` [RESEND v22 3/3] pwm: Add OpenCores PTC PWM driver Hal Feng
2026-08-12 8:52 ` Hal Feng
2026-09-07 19:07 ` [RESEND v22 0/3] Add OpenCores PTC PWM support Maud Spierings
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