Re: [PATCH v5 7/8] arm64: dts: renesas: r9a09g077: Use CPG/MSSR syscon for WDTDCR access

[sashiko-bot@kernel.org]

Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider:
- [High] The transition to using a syscon regmap for WDTDCR access is broken, preventing the watchdog from probing and containing an out-of-bounds regmap access flaw.
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commit 0e87a2089f722e3ac7bcab46cff76d445536d9fd
Author: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Subject: arm64: dts: renesas: r9a09g077: Use CPG/MSSR syscon for WDTDCR access

This patch replaces the direct mapping of individual WDTDCR registers for
watchdogs wdt0-wdt5 with a new "renesas,sysc" phandle property pointing
to the CPG/MSSR block. The watchdog driver is expected to use a unified
syscon regmap interface for these accesses.

> diff --git a/arch/arm64/boot/dts/renesas/r9a09g077.dtsi b/arch/arm64/boot/dts/renesas/r9a09g077.dtsi
> index 40494159831d8..ad5189d55cef2 100644
> --- a/arch/arm64/boot/dts/renesas/r9a09g077.dtsi
> +++ b/arch/arm64/boot/dts/renesas/r9a09g077.dtsi
> @@ -327,61 +327,61 @@ channel1 {
>  
>  		wdt0: watchdog@80082000 {
>  			compatible = "renesas,r9a09g077-wdt";
> -			reg = <0 0x80082000 0 0x400>,
> -			      <0 0x81295100 0 0x04>;
> +			reg = <0 0x80082000 0 0x400>;
>  			clocks = <&cpg CPG_CORE R9A09G077_CLK_PCLKL>;
>  			clock-names = "pclk";
>  			power-domains = <&cpg>;
> +			renesas,sysc = <&cpg 0>;

[Severity: High]
Does this node successfully acquire a syscon regmap from the cpg node?

The cpg node lacks the "syscon" compatible string in its definition:

		cpg: clock-controller@80280000 {
			compatible = "renesas,r9a09g077-cpg-mssr";
			reg = <0 0x80280000 0 0x10000>,
			      <0 0x81280000 0 0x10000>;
			...
		};

Without the "syscon" compatible string, syscon_node_to_regmap() will return
-EPROBE_DEFER indefinitely, preventing the watchdog driver from probing.

Furthermore, will the generic syscon regmap allow access to the WDTDCR
registers in the second memory region?

The generic syscon framework only maps the first reg resource region, which
the cpg node defines as 0x10000 bytes. The watchdog driver calculates a
WDTDCR offset of 0x15100 via:

drivers/watchdog/rzv2h_wdt.c:RZT2H_SYS_BLOCK1()
#define RZT2H_SYS_BLOCK1(n)	(BIT(16) | (0x5100 + (n) * 4))

This offset exceeds the max_register limit (0xFFFC) of the generic syscon
regmap. When rzt2h_wdt_wdtdcr_count_stop() passes this offset to
regmap_set_bits(), the regmap core will reject the write with -EINVAL.

>  			status = "disabled";
>  		};

[ ... ]

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Sashiko AI review · https://sashiko.dev/#/patchset/20260911111731.3404308-1-prabhakar.mahadev-lad.rj@bp.renesas.com?part=7