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[199.106.103.52]) by smtp.gmail.com with ESMTPSA id 00721157ae682-884895001fasm10483237b3.45.2026.09.11.07.21.10 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 11 Sep 2026 07:21:14 -0700 (PDT) From: Shawn Guo To: Bjorn Andersson Cc: Konrad Dybcio , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Bartosz Golaszewski , Krishna Kurapati , devicetree@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, Bartosz Golaszewski , Shawn Guo Subject: [PATCH 3/5] arm64: dts: qcom: nord-embedded: Add USB resources and PHYs Date: Fri, 11 Sep 2026 22:20:38 +0800 Message-ID: <20260911142040.100263-4-shengchao.guo@oss.qualcomm.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260911142040.100263-1-shengchao.guo@oss.qualcomm.com> References: <20260911142040.100263-1-shengchao.guo@oss.qualcomm.com> Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Proofpoint-GUID: N0ckILH6t7lgDmzQ4axA9ahLC4jdx_rc X-Authority-Analysis: v=2.4 cv=PLmaavqC c=1 sm=1 tr=0 ts=6aa40e5c cx=c_pps a=g1v0Z557R90hA0UpD/5Yag==:117 a=b9+bayejhc3NMeqCNyeLQQ==:17 a=VdqzKS8jKosA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=rJkE3RaqiGZ5pbrm-msn:22 a=EUspDBNiAAAA:8 a=NOSK86ayaCRT3GQFxdkA:9 a=MFSWADHSvvjO3QEy5MdX:22 X-Proofpoint-ORIG-GUID: N0ckILH6t7lgDmzQ4axA9ahLC4jdx_rc X-Proofpoint-Spam-Info: AW1haW4tMjYwOTExMDIwMSBTYWx0ZWRfX90VT6Z/DRwHa KqH3h7gEbr6zjZONfVKG2sZN73I5GutsASuFXzU+MvN93Zy2IvHCmEfi8bmCzDfaCeCzrq76uTy 4laBoVjA1qyxrgpRmmCSf8o8oL7V3JU= X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwOTExMDIwMSBTYWx0ZWRfX1hTWh1eVq/yi fg7dN54x672aaKE+RLtGyNxwqmVhoCAbDD6LG/5xHJos/i54QVWB56puBXfwUC5c6HBnp2w3xRz 20XFDxEh9QkeNpRhQzOCwiP8jGT2lpO6yCZu0KvPlRdILbHnQHoQFWQQAPy5oC0V3OyF7t2nwOd d1Wco4zMr6Iup6ZRs3tq25V9pu5NGLArjjybjYUrhZlyPDkUyxPqkOWShJ31Tntb7ZKRymbqCwG AGoWWFjQ46S48FbbShllCQcWtS4obco+oxbaqK3euVigXt+7jEX7ULwPYLzaIBefAlL7Uqj6VdL rWBzjGbb+BDMlCNYtmbIdDC6S0vLBQ03Ehd4hocrhz4ynDHJgN+FK5AP6aHKwjQFWevdreBFmHE DF7i9dZsAA86ggGdzcGVx9ur9mQmeQyC+X/0EI+QxJKx96XVl2ZAIYZ13NzImSCmdSX6iouF7Xq BbI9t5HnEE4kmhDyN+g== X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1176,Hydra:6.1.134,FMLib:17.12.100.49 definitions=2026-09-11_04,2026-09-11_01,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 bulkscore=0 suspectscore=0 spamscore=0 phishscore=0 adultscore=0 malwarescore=0 clxscore=1015 priorityscore=1501 impostorscore=0 lowpriorityscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2609040000 definitions=main-2609110201 From: Bartosz Golaszewski Add the platform resources for the three USB controllers on the embedded Nord variant: clocks, resets, power domains and interconnect paths. Add the eUSB2 PHY for each of the three controllers, plus the QMP combo PHYs for USB_0 and USB_1, and feed the two QMP USB3 pipe clocks back into negcc, which so far carried placeholder zeros in their place. The eUSB2 PHY of instance 2 gets no 'resets': the SoC provides only two QUSB2PHY block resets, belonging to instances 0 and 1. Instance 2 comes out of reset with the rest of the USB20 tile, driven by the controller. Signed-off-by: Bartosz Golaszewski Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/qcom/nord-embedded.dtsi | 307 +++++++++++++++++++- 1 file changed, 305 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/nord-embedded.dtsi b/arch/arm64/boot/dts/qcom/nord-embedded.dtsi index c7ac2e66632e..84ce57a07361 100644 --- a/arch/arm64/boot/dts/qcom/nord-embedded.dtsi +++ b/arch/arm64/boot/dts/qcom/nord-embedded.dtsi @@ -11,6 +11,7 @@ #include #include #include +#include #include #include @@ -842,6 +843,162 @@ hpass_ag_noc: interconnect@5fc0000 { qcom,bcm-voters = <&apps_bcm_voter>; }; + usb_2_hsphy: phy@88e0000 { + compatible = "qcom,nord-snps-eusb2-phy", + "qcom,sm8550-snps-eusb2-phy"; + reg = <0x0 0x088e0000 0x0 0x154>; + + clocks = <&tcsrcc TCSR_USB2_2_CLKREF_EN>; + clock-names = "ref"; + + /* + * The SoC has three eUSB2 PHYs but only two QUSB2PHY block + * resets, which belong to instances 0 and 1 (usb_0 and usb_1). + * This PHY, instance 2, has none of its own: it is taken out of + * reset together with the rest of the USB20 tile by + * NE_GCC_USB20_PRIM_BCR, which the controller owns and pulses + * before touching any register. So no 'resets' here - both + * consumers would need that single reset exclusively. + */ + + #phy-cells = <0>; + + status = "disabled"; + }; + + usb_0_qmpphy: phy@88e1000 { + compatible = "qcom,nord-qmp-usb3-dp-phy"; + reg = <0x0 0x088e1000 0x0 0x3000>; + + clocks = <&negcc NE_GCC_USB3_PRIM_PHY_AUX_CLK>, + <&tcsrcc TCSR_USB3_0_CLKREF_EN>, + <&negcc NE_GCC_USB3_PRIM_PHY_COM_AUX_CLK>, + <&negcc NE_GCC_USB3_PRIM_PHY_PIPE_CLK>; + clock-names = "aux", + "ref", + "com_aux", + "usb3_pipe"; + + power-domains = <&negcc NE_GCC_USB3_PHY_GDSC>; + + resets = <&negcc NE_GCC_USB3_PHY_PRIM_BCR>, + <&negcc NE_GCC_USB3_DP_PHY_PRIM_BCR>; + reset-names = "phy", + "common"; + + #clock-cells = <1>; + #phy-cells = <1>; + + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + #address-cells = <1>; + #size-cells = <0>; + + usb_0_qmpphy_usb_ss_out: endpoint@1 { + reg = <1>; + data-lanes = <1 0>; + }; + }; + + port@1 { + reg = <1>; + + usb_0_qmpphy_usb_ss_in: endpoint { + remote-endpoint = <&usb_0_dwc3_ss>; + }; + }; + }; + }; + + usb_1_qmpphy: phy@88e4000 { + compatible = "qcom,nord-qmp-usb3-dp-phy"; + reg = <0x0 0x088e4000 0x0 0x3000>; + + clocks = <&negcc NE_GCC_USB3_SEC_PHY_AUX_CLK>, + <&tcsrcc TCSR_USB3_1_CLKREF_EN>, + <&negcc NE_GCC_USB3_SEC_PHY_COM_AUX_CLK>, + <&negcc NE_GCC_USB3_SEC_PHY_PIPE_CLK>; + clock-names = "aux", + "ref", + "com_aux", + "usb3_pipe"; + + power-domains = <&negcc NE_GCC_USB3_SEC_PHY_GDSC>; + + resets = <&negcc NE_GCC_USB3_PHY_SEC_BCR>, + <&negcc NE_GCC_USB3_DP_PHY_SEC_BCR>; + reset-names = "phy", + "common"; + + #clock-cells = <1>; + #phy-cells = <1>; + + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + #address-cells = <1>; + #size-cells = <0>; + + /* Same as usb_0_qmpphy above. */ + usb_1_qmpphy_usb_ss_out: endpoint@1 { + reg = <1>; + data-lanes = <1 0>; + }; + }; + + port@1 { + reg = <1>; + + usb_1_qmpphy_usb_ss_in: endpoint { + remote-endpoint = <&usb_1_dwc3_ss>; + }; + }; + }; + }; + + usb_0_hsphy: phy@88ea000 { + compatible = "qcom,nord-snps-eusb2-phy", + "qcom,sm8550-snps-eusb2-phy"; + reg = <0x0 0x088ea000 0x0 0x154>; + + clocks = <&tcsrcc TCSR_USB2_0_CLKREF_EN>; + clock-names = "ref"; + + resets = <&negcc NE_GCC_QUSB2PHY_PRIM_BCR>; + + #phy-cells = <0>; + + status = "disabled"; + }; + + usb_1_hsphy: phy@88eb000 { + compatible = "qcom,nord-snps-eusb2-phy", + "qcom,sm8550-snps-eusb2-phy"; + reg = <0x0 0x088eb000 0x0 0x154>; + + clocks = <&tcsrcc TCSR_USB2_1_CLKREF_EN>; + clock-names = "ref"; + + resets = <&negcc NE_GCC_QUSB2PHY_SEC_BCR>; + + #phy-cells = <0>; + + status = "disabled"; + }; + negcc: clock-controller@8900000 { compatible = "qcom,nord-negcc"; reg = <0x0 0x08900000 0x0 0xf4200>; @@ -850,8 +1007,8 @@ negcc: clock-controller@8900000 { <0>, <0>, <0>, - <0>, - <0>; + <&usb_1_qmpphy QMP_USB43DP_USB3_PIPE_CLK>, + <&usb_0_qmpphy QMP_USB43DP_USB3_PIPE_CLK>; #clock-cells = <1>; #reset-cells = <1>; #power-domain-cells = <1>; @@ -1881,3 +2038,149 @@ opp-403000000 { }; }; }; + +&usb_0 { + clocks = <&negcc NE_GCC_CNOC_USB3_PRIM_AXI_CLK>, + <&negcc NE_GCC_USB31_PRIM_MASTER_CLK>, + <&negcc NE_GCC_AGGRE_NOC_USB3_PRIM_AXI_CLK>, + <&negcc NE_GCC_USB31_PRIM_SLEEP_CLK>, + <&negcc NE_GCC_USB31_PRIM_MOCK_UTMI_CLK>, + <&tcsrcc TCSR_USB3_0_CLKREF_EN>; + clock-names = "cfg_noc", + "core", + "iface", + "sleep", + "mock_utmi", + "xo"; + + assigned-clocks = <&negcc NE_GCC_USB31_PRIM_MOCK_UTMI_CLK>, + <&negcc NE_GCC_USB31_PRIM_MASTER_CLK>; + assigned-clock-rates = <19200000>, <200000000>; + + power-domains = <&negcc NE_GCC_USB31_PRIM_GDSC>; + required-opps = <&rpmhpd_opp_nom>; + + resets = <&negcc NE_GCC_USB31_PRIM_BCR>; + + interconnects = <&aggre1_noc_tile MASTER_USB3_0 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, + <&hscnoc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS + &config_noc SLAVE_USB3_0 QCOM_ICC_TAG_ALWAYS>; + interconnect-names = "usb-ddr", + "apps-usb"; + + phys = <&usb_0_hsphy>, + <&usb_0_qmpphy QMP_USB43DP_USB3_PHY>; + phy-names = "usb2-phy", + "usb3-phy"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + usb_0_dwc3_hs: endpoint { + }; + }; + + port@1 { + reg = <1>; + + usb_0_dwc3_ss: endpoint { + remote-endpoint = <&usb_0_qmpphy_usb_ss_in>; + }; + }; + }; +}; + +&usb_1 { + clocks = <&negcc NE_GCC_CNOC_USB3_SEC_AXI_CLK>, + <&negcc NE_GCC_USB31_SEC_MASTER_CLK>, + <&negcc NE_GCC_AGGRE_NOC_USB3_SEC_AXI_CLK>, + <&negcc NE_GCC_USB31_SEC_SLEEP_CLK>, + <&negcc NE_GCC_USB31_SEC_MOCK_UTMI_CLK>, + <&tcsrcc TCSR_USB3_1_CLKREF_EN>; + clock-names = "cfg_noc", + "core", + "iface", + "sleep", + "mock_utmi", + "xo"; + + assigned-clocks = <&negcc NE_GCC_USB31_SEC_MOCK_UTMI_CLK>, + <&negcc NE_GCC_USB31_SEC_MASTER_CLK>; + assigned-clock-rates = <19200000>, <200000000>; + + power-domains = <&negcc NE_GCC_USB31_SEC_GDSC>; + required-opps = <&rpmhpd_opp_nom>; + + resets = <&negcc NE_GCC_USB31_SEC_BCR>; + + interconnects = <&aggre1_noc_tile MASTER_USB3_1 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, + <&hscnoc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS + &config_noc SLAVE_USB3_1 QCOM_ICC_TAG_ALWAYS>; + interconnect-names = "usb-ddr", + "apps-usb"; + + phys = <&usb_1_hsphy>, + <&usb_1_qmpphy QMP_USB43DP_USB3_PHY>; + phy-names = "usb2-phy", + "usb3-phy"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + usb_1_dwc3_hs: endpoint { + }; + }; + + port@1 { + reg = <1>; + + usb_1_dwc3_ss: endpoint { + remote-endpoint = <&usb_1_qmpphy_usb_ss_in>; + }; + }; + }; +}; + +&usb_2 { + clocks = <&negcc NE_GCC_CNOC_USB2_AXI_CLK>, + <&negcc NE_GCC_USB20_MASTER_CLK>, + <&negcc NE_GCC_AGGRE_NOC_USB2_AXI_CLK>, + <&negcc NE_GCC_USB20_SLEEP_CLK>, + <&negcc NE_GCC_USB20_MOCK_UTMI_CLK>, + <&tcsrcc TCSR_USB2_2_CLKREF_EN>; + clock-names = "cfg_noc", + "core", + "iface", + "sleep", + "mock_utmi", + "xo"; + + assigned-clocks = <&negcc NE_GCC_USB20_MOCK_UTMI_CLK>, + <&negcc NE_GCC_USB20_MASTER_CLK>; + assigned-clock-rates = <19200000>, <120000000>; + + power-domains = <&negcc NE_GCC_USB20_PRIM_GDSC>; + required-opps = <&rpmhpd_opp_nom>; + + resets = <&negcc NE_GCC_USB20_PRIM_BCR>; + + interconnects = <&aggre1_noc_tile MASTER_USB2 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, + <&hscnoc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS + &config_noc SLAVE_USB2 QCOM_ICC_TAG_ALWAYS>; + interconnect-names = "usb-ddr", + "apps-usb"; + + phys = <&usb_2_hsphy>; + phy-names = "usb2-phy"; +}; -- 2.43.0