Re: [PATCH 0/5] Add ADC support for RZ/G3L TSU

[Jonathan Cameron <jic23@kernel.org>]

On Fri, 11 Sep 2026 14:36:43 +0100
Biju Das <biju.das.jz@bp.renesas.com> wrote:

> On the RZ/G3L, ADC1 is connected to the TSU, whereas it is connected to
> ADC0 on the RZ/G3S. There are no ADCR0 to ADCR7 registers on the RZ/G3L,
> and the INTEN bits in the ADINT registers are also different. Add ADC
> support for the TSU (a.k.a. ADC1).

Too many TLA.  What is TSU?  In general write this for someone who
is not really that familiar with the particular part!

> 
> The SoC dtsi patch depends on [1]
> [1] https://lore.kernel.org/all/20260911131629.111564-2-biju.das.jz@bp.renesas.com/
> 
> Biju Das (5):
>   dt-bindings: iio: adc: renesas,rzg2l-adc: Make '#io-channel-cells'
>     required for R9A08G045
>   dt-bindings: iio: adc: renesas,rzg2l-adc: Document RZ/G3L ADC for TSU
>   iio: adc: rzg2l_adc: Add RZ/G3L ADC support for TSU
>   clk: renesas: r9a08g046: Add TSU,ADC1 clocks and reset
>   arm64: dts: renesas: r9a08g046: Enable TSU
> 
>  .../bindings/iio/adc/renesas,rzg2l-adc.yaml   | 28 +++++++-
>  arch/arm64/boot/dts/renesas/r9a08g046.dtsi    | 66 +++++++++++++++++++
>  drivers/clk/renesas/r9a08g046-cpg.c           | 10 +++
>  drivers/iio/adc/rzg2l_adc.c                   |  9 +++
>  4 files changed, 112 insertions(+), 1 deletion(-)
>