From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from bali.collaboradmins.com (bali.collaboradmins.com [148.251.105.195]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 9A67444999F; Mon, 14 Sep 2026 11:39:23 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=148.251.105.195 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1789385965; cv=none; b=GhnukFE3Twt7WgvpusUedXsNeyMIzBQSUBa8vECJDQ+4Al57zoHExARyXoBLCBTPYdl87j+DAQFiU7nT66FqVHpL6Z0XlygntNbEE/6YwodENlJUsd3OCZrO4U+oZ3THZW17Q90giNuNNJLNJF2ykXBxnXY9wg7iZfILiss6hWQ= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1789385965; c=relaxed/simple; bh=u/D/WxpbgbGO/YXlEsLYW2eKlLgsf5ydTcbshi4YT0w=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=A4XkL5MCA0l7sDE0o+mWqVxCcJALF4F7zl6Ml6YVepEP+p/Tk/YedQbuNI850iPKqerkzdwG7ep0BjVU0Yn44nyHVxJQMlfl75tMFKduHPljfPxe/wFqZwIQejwFNoOp7vh1zdGzy/i7b0GnvH9yFmcbzSbBrW8b8hhghrKNWN4= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=collabora.com; spf=pass smtp.mailfrom=collabora.com; dkim=pass (2048-bit key) header.d=collabora.com header.i=@collabora.com header.b=fqclG8YU; arc=none smtp.client-ip=148.251.105.195 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=collabora.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=collabora.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=collabora.com header.i=@collabora.com header.b="fqclG8YU" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=collabora.com; s=mail; t=1789385961; bh=u/D/WxpbgbGO/YXlEsLYW2eKlLgsf5ydTcbshi4YT0w=; h=From:Date:Subject:References:In-Reply-To:To:Cc:From; b=fqclG8YUMYkfHp2h0jAhsuuv8JPsM3AgG9/OngCGjzzUWDtmZRzotYRUv/l9NrNGe maZmb2lH/Ze8IE6nBihEXuKjcHoOY1/noWG4SYlqOoWD2fPrYTkCEB7N20Motd85OD TzniyQZuUZkedW8fMIMZbLq5xMVAI8Rt2odrl91OGz/2Yc5F0BlEJparOSdOc3F81n 840wHe0HWrQsE276F2Qyzn707h3fgkH/T6Y8bDAvtc8uMPm7sAGh9xo/w4fkM+67NJ kT+80C+G1K63fMUzrzzAUa56Yvv2oZpp3UG93i+Zk3OlXpL6pCTvHZo0q7yxYjrwns +2KxuMMgUMiuQ== Received: from yukiji.home (unknown [100.64.0.131]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange x25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) (Authenticated sender: laeyraud) by bali.collaboradmins.com (Postfix) with ESMTPSA id 05B6A17E0D7F; Mon, 14 Sep 2026 13:39:19 +0200 (CEST) From: Louis-Alexis Eyraud Date: Mon, 14 Sep 2026 13:38:54 +0200 Subject: [PATCH v12 08/24] scsi: ufs: mediatek: Add dual 0.9V supply support Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: 7bit Message-Id: <20260914-mt8196-ufs-v12-8-9279d7ef814d@collabora.com> References: <20260914-mt8196-ufs-v12-0-9279d7ef814d@collabora.com> In-Reply-To: <20260914-mt8196-ufs-v12-0-9279d7ef814d@collabora.com> To: Chunfeng Yun , Vinod Koul , Neil Armstrong , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Matthias Brugger , AngeloGioacchino Del Regno , Peter Wang , Chaotian Jing , Alim Akhtar , Avri Altman , Bart Van Assche , Stanley Jhu , "James E.J. Bottomley" , Philipp Zabel , Liam Girdwood , Mark Brown , Manivannan Sadhasivam , "Martin K. Petersen" Cc: kernel@collabora.com, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, linux-phy@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-scsi@vger.kernel.org, Nicolas Frattaroli , Louis-Alexis Eyraud X-Mailer: b4 0.14.3 X-Developer-Signature: v=1; a=ed25519-sha256; t=1789385943; l=4943; i=louisalexis.eyraud@collabora.com; s=20250113; h=from:subject:message-id; bh=u/D/WxpbgbGO/YXlEsLYW2eKlLgsf5ydTcbshi4YT0w=; b=/rmDKEQpUgBouArhObVXszVEI3XupxFdk0IKNThH6PuLr3m00GlHRkEIpOiKcD92oY3jZK3d2 DJ4SDDXWhjLBD579kj3AZRKeEjaINNkbVGSCbzpO+gvD0fwQhm8PW4s X-Developer-Key: i=louisalexis.eyraud@collabora.com; a=ed25519; pk=CHFBDB2Kqh4EHc6JIqFn69GhxJJAzc0Zr4e8QxtumuM= The MT8196 SoC has an additional pin in comparison of the MT8183 SoC, that is used to feed the host controller with a 0.9V supply. In preparation of this SoC support, add in platform data and driver the management a second optional 0.9V regulator named "avdd09-1". Signed-off-by: Louis-Alexis Eyraud --- drivers/ufs/host/ufs-mediatek.c | 91 ++++++++++++++++++++++++++++++----------- drivers/ufs/host/ufs-mediatek.h | 1 + 2 files changed, 69 insertions(+), 23 deletions(-) diff --git a/drivers/ufs/host/ufs-mediatek.c b/drivers/ufs/host/ufs-mediatek.c index f43bee50adb2..467fc77c90e1 100644 --- a/drivers/ufs/host/ufs-mediatek.c +++ b/drivers/ufs/host/ufs-mediatek.c @@ -41,6 +41,7 @@ static void _ufs_mtk_clk_scale(struct ufs_hba *hba, bool scale_up); struct ufs_mtk_soc_data { bool has_avdd09; + bool has_avdd09_1; }; static const struct ufs_dev_quirk ufs_mtk_dev_fixups[] = { @@ -513,18 +514,37 @@ static int ufs_mtk_wait_link_state(struct ufs_hba *hba, u32 state, static int ufs_mtk_09v_off(struct ufs_mtk_host *host) { struct arm_smccc_res res; - int ret; + int ret, ret2; - if (!host->reg_avdd09) + if (!host->reg_avdd09 && !host->reg_avdd09_1) return 0; ufs_mtk_va09_pwr_ctrl(res, 0); - ret = regulator_disable(host->reg_avdd09); - if (ret) { - dev_err(host->hba->dev, "Failed to disable avdd09-supply: %pe\n", - ERR_PTR(ret)); - ufs_mtk_va09_pwr_ctrl(res, 1); - return ret; + + if (host->reg_avdd09) { + ret = regulator_disable(host->reg_avdd09); + if (ret) { + dev_err(host->hba->dev, "Failed to disable avdd09-supply: %pe\n", + ERR_PTR(ret)); + ufs_mtk_va09_pwr_ctrl(res, 1); + return ret; + } + } + + if (host->reg_avdd09_1) { + ret = regulator_disable(host->reg_avdd09_1); + if (ret) { + dev_err(host->hba->dev, "Failed to disable avdd09-1-supply: %pe\n", + ERR_PTR(ret)); + + ret2 = regulator_enable(host->reg_avdd09); + if (ret2) + dev_err(host->hba->dev, "Failed to re-enable avdd09-supply: %pe\n", + ERR_PTR(ret2)); + + ufs_mtk_va09_pwr_ctrl(res, 1); + return ret; + } } return 0; @@ -535,14 +555,26 @@ static int ufs_mtk_09v_on(struct ufs_mtk_host *host) struct arm_smccc_res res; int ret; - if (!host->reg_avdd09) + if (!host->reg_avdd09 && !host->reg_avdd09_1) return 0; - ret = regulator_enable(host->reg_avdd09); - if (ret) { - dev_err(host->hba->dev, "Failed to enable avdd09-supply: %pe\n", - ERR_PTR(ret)); - return ret; + if (host->reg_avdd09) { + ret = regulator_enable(host->reg_avdd09); + if (ret) { + dev_err(host->hba->dev, "Failed to enable avdd09-supply: %pe\n", + ERR_PTR(ret)); + return ret; + } + } + + if (host->reg_avdd09_1) { + ret = regulator_enable(host->reg_avdd09_1); + if (ret) { + dev_err(host->hba->dev, "Failed to enable avdd09-1-supply: %pe\n", + ERR_PTR(ret)); + regulator_disable(host->reg_avdd09); + return ret; + } } ufs_mtk_va09_pwr_ctrl(res, 1); @@ -1232,20 +1264,33 @@ static int ufs_mtk_get_supplies(struct ufs_mtk_host *host) struct device *dev = host->hba->dev; const struct ufs_mtk_soc_data *data = of_device_get_match_data(dev); - if (!data || !data->has_avdd09) + if (!data) return 0; - host->reg_avdd09 = devm_regulator_get_optional(dev, "avdd09"); - if (IS_ERR(host->reg_avdd09)) { - if (PTR_ERR(host->reg_avdd09) == -ENODEV) { + if (data->has_avdd09) { + host->reg_avdd09 = devm_regulator_get_optional(dev, "avdd09"); + if (IS_ERR(host->reg_avdd09)) { + if (PTR_ERR(host->reg_avdd09) != -ENODEV) { + return dev_err_probe(dev, + PTR_ERR(host->reg_avdd09), + "Failed to get avdd09 regulator: %pe\n", + host->reg_avdd09); + } host->reg_avdd09 = NULL; - return 0; } + } - return dev_err_probe(dev, - PTR_ERR(host->reg_avdd09), - "Failed to get avdd09 regulator: %pe\n", - host->reg_avdd09); + if (data->has_avdd09_1) { + host->reg_avdd09_1 = devm_regulator_get_optional(dev, "avdd09-1"); + if (IS_ERR(host->reg_avdd09_1)) { + if (PTR_ERR(host->reg_avdd09_1) != -ENODEV) { + return dev_err_probe(dev, + PTR_ERR(host->reg_avdd09_1), + "Failed to get avdd09-1 regulator: %pe\n", + host->reg_avdd09_1); + } + host->reg_avdd09_1 = NULL; + } } return 0; diff --git a/drivers/ufs/host/ufs-mediatek.h b/drivers/ufs/host/ufs-mediatek.h index c63740b98e85..477fb9e36555 100644 --- a/drivers/ufs/host/ufs-mediatek.h +++ b/drivers/ufs/host/ufs-mediatek.h @@ -176,6 +176,7 @@ struct ufs_mtk_mcq_intr_info { struct ufs_mtk_host { struct phy *mphy; struct regulator *reg_avdd09; + struct regulator *reg_avdd09_1; struct reset_control_bulk_data resets[MTK_UFS_NUM_RESETS]; struct ufs_hba *hba; struct ufs_mtk_crypt_cfg *crypt; -- 2.55.0