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[60.250.196.139]) by smtp.gmail.com with ESMTPSA id 98e67ed59e1d1-39d9540fd76sm22996627a91.9.2026.09.14.04.07.43 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 14 Sep 2026 04:07:45 -0700 (PDT) From: Chi-Wen Weng To: ukleinek@kernel.org, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org Cc: linux-arm-kernel@lists.infradead.org, linux-pwm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, cwweng@nuvoton.com, cwweng.linux@gmail.com Subject: [PATCH v6 0/2] pwm: Add Nuvoton MA35D1 PWM controller support Date: Mon, 14 Sep 2026 19:07:37 +0800 Message-Id: <20260914110739.203479-1-cwweng.linux@gmail.com> X-Mailer: git-send-email 2.25.1 Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit From: Chi-Wen Weng This series adds the device tree binding and PWM framework driver for the Nuvoton MA35D1 EPWM controller. The MA35D1 EPWM controller provides 6 PWM channels. The hardware supports up, down and up-down counter types, auto-reload and one-shot modes, and independent and complementary output modes. The initial driver supports independent output mode only and configures a channel for up-counting and auto-reload operation when an explicit .apply() request is made. The waveform generator drives the output high at the zero point and low at the compare-up point. In up-counting mode, the counter counts from 0 to PERIOD inclusive. With the selected waveform actions, CMPDAT = 0 generates a 0% duty cycle and CMPDAT > PERIOD generates a 100% duty cycle. The driver keeps PERIOD one count below the 16-bit field maximum so that CMPDAT can be programmed greater than PERIOD for the full-duty case. PERIOD and CMPDAT use the hardware period-loading buffers. Since the two registers are written separately, if a period boundary occurs between the writes, one transitional cycle can use the new PERIOD value with the previous CMPDAT value. The following period then uses both new values. The driver selects period loading mode by clearing IMMLDENn, WINLDENn and CTRLDn. When a PWM is disabled, POENn and CNTENn are cleared. Clearing POENn disables the output driver and puts the output pin into high impedance. The driver does not modify the PWM controller during probe. This preserves PWM outputs that may have been configured and enabled by firmware, such as a display backlight. The counter and waveform configuration is changed only for the channel passed to .apply(). Since the independent/complementary mode selection is shared by each pair of channels, the driver refuses to change an active complementary pair to independent mode when the paired channel is active. Changes in v6: - Document that clearing POENn disables the output driver and puts the output pin into high impedance. - Document that a period boundary between the PERIOD and CMPDAT writes can result in one transitional cycle using the new period with the previous duty cycle. - No functional changes. Changes in v5: - Remove the probe-time controller initialization to preserve PWM outputs configured by firmware. - Configure the counter and waveform settings only for the channel passed to .apply(). - Keep the disable path limited to clearing POENn and CNTENn. - Check for an active paired channel before changing a complementary pair to independent mode. - Return -EBUSY when changing the shared output mode would disturb an active paired channel. - Document that the initial driver supports independent output mode only. - Remove the unnecessary include. - Simplify the WGCTL action field handling and remove the associated static inline mask helpers. - Rename the PWM field and period limits to clarify their different semantics. - Configure period loading mode explicitly in .apply(). - Preserve the pair-shared clock prescaler and account for it in period and duty-cycle calculations. - Limit the period to 0xffff counter cycles while reserving CMPDAT = 0xffff for the full-duty case. Changes in v4: - Add a Limitations section to describe the hardware capabilities and driver limitations. - Add a link to the MA35D1 reference manual. - Replace register address macros containing the base pointer with register offset macros. - Add readl/writel/rmw helper functions. - Rename TOTAL_CHANNELS to NUM_CHANNELS. - Use unsigned long for the cached clock rate. - Use devm_clk_rate_exclusive_get(). - Configure polarity before enabling the counter and output. - Add controller initialization for up-counting, auto-reload and independent output mode. - Configure the waveform generator for zero-point-high and compare-up-low output. - Fix the period conversion because the hardware period is PERIOD + 1 cycles. - Limit the maximum PERIOD value to 0xfffe so that CMPDAT = 0xffff can be used to generate 100% duty cycle. - Use CNTEN and POEN bits to report the enabled state in .get_state(). - Disable the PWM by clearing POENn and CNTENn. - Fix error message capitalization and trailing newlines. - Fix coding style issues reported by review/checkpatch-style tools. Changes in v3: - Update nuvoton,ma35d1-pwm.yaml: - Add maintainers entry. - Increase "#pwm-cells" to 3. - Update the MA35D1 PWM driver: - Organize include headers and macro definitions. - Rename REG_PWM_XXXX macros to MA35D1_REG_PWM_XXXX. - Add register address macros. v2 resend: - Remove incorrect Reviewed-by tags. Changes in v2: - Update nuvoton,ma35d1-pwm.yaml: - Fix maxItems of reg to 1. - Remove unused label. - Update the MA35D1 PWM driver: - Remove MODULE_ALIAS(). - Add chip->atomic = true. Chi-Wen Weng (2): dt-bindings: pwm: Add Nuvoton MA35D1 PWM controller pwm: Add Nuvoton MA35D1 PWM controller support Documentation/devicetree/bindings/pwm/nuvoton,ma35d1-pwm.yaml | 45 +++ drivers/pwm/Kconfig | 10 + drivers/pwm/Makefile | 1 + drivers/pwm/pwm-ma35d1.c | 387 +++++++++++++++++++++ 4 files changed, 443 insertions(+) create mode 100644 Documentation/devicetree/bindings/pwm/nuvoton,ma35d1-pwm.yaml create mode 100644 drivers/pwm/pwm-ma35d1.c -- 2.25.1