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[2a01:cb00:7c5:9900:d73f:8285:c1e6:47ab]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-49e7d2a94b9sm58001325e9.3.2026.09.15.03.43.30 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 15 Sep 2026 03:43:30 -0700 (PDT) From: Amin Gattout Date: Tue, 15 Sep 2026 12:42:48 +0200 Subject: [PATCH v2 3/4] phy: rockchip: phy-rockchip-inno-csidphy: add support for rk3576 variant Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: 7bit Message-Id: <20260915-rk3576-dphy-v2-3-b56e68b54b8c@gmail.com> References: <20260915-rk3576-dphy-v2-0-b56e68b54b8c@gmail.com> In-Reply-To: <20260915-rk3576-dphy-v2-0-b56e68b54b8c@gmail.com> To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Heiko Stuebner , Vinod Koul , Neil Armstrong Cc: Michael Riesch , devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org, linux-kernel@vger.kernel.org, linux-phy@lists.infradead.org, Amin Gattout X-Mailer: b4 0.16.0 X-Developer-Signature: v=1; a=ed25519-sha256; t=1789469006; l=1842; i=amin.gattout@gmail.com; s=20260818; h=from:subject:message-id; bh=T7svtQCEZR4NbRSxQOr575LmZrX+L5qTFSBrf8JfOqc=; b=eQvDxheF72tsvAJS32ZkaFvXX6NNWm28Bsw7F/w1Zy5QmGsgwEi4egtVnZZRjBKNhf4WjFbAW h0O3gsraYFIAa6PT+HoD2V4W8Tz+gYMZVjRPi9SOtZsJl8Lzfm0kax8 X-Developer-Key: i=amin.gattout@gmail.com; a=ed25519; pk=MSIqDPkCOkwtyP8Fns1m+KFU9SgqoDl2mpLe18vL+hQ= The two RK3576 MIPI CSI-2 DPHYs can be supported using the existing phy-rockchip-inno-csidphy driver, but they need their own driver data: as on RK3588 the GRF control bits live in a dedicated CSI-DPHY GRF at offset 0x0, while each PHY instance only has an APB reset line, as on RK3568. Signed-off-by: Amin Gattout --- drivers/phy/rockchip/phy-rockchip-inno-csidphy.c | 15 +++++++++++++++ 1 file changed, 15 insertions(+) diff --git a/drivers/phy/rockchip/phy-rockchip-inno-csidphy.c b/drivers/phy/rockchip/phy-rockchip-inno-csidphy.c index c79fb53d8ee5..177beb685f70 100644 --- a/drivers/phy/rockchip/phy-rockchip-inno-csidphy.c +++ b/drivers/phy/rockchip/phy-rockchip-inno-csidphy.c @@ -403,6 +403,17 @@ static const struct dphy_drv_data rk3568_mipidphy_drv_data = { .resets_num = ARRAY_SIZE(rk3368_reset_names), }; +static const struct dphy_drv_data rk3576_mipidphy_drv_data = { + .pwrctl_offset = -1, + .ths_settle_offset = RK3568_CSIDPHY_CLK_WR_THS_SETTLE, + .calib_offset = RK3568_CSIDPHY_CLK_CALIB_EN, + .hsfreq_ranges = rk1808_mipidphy_hsfreq_ranges, + .num_hsfreq_ranges = ARRAY_SIZE(rk1808_mipidphy_hsfreq_ranges), + .grf_regs = rk3588_grf_dphy_regs, + .resets = rk3368_reset_names, + .resets_num = ARRAY_SIZE(rk3368_reset_names), +}; + static const struct dphy_drv_data rk3588_mipidphy_drv_data = { .pwrctl_offset = -1, .ths_settle_offset = RK3568_CSIDPHY_CLK_WR_THS_SETTLE, @@ -435,6 +446,10 @@ static const struct of_device_id rockchip_inno_csidphy_match_id[] = { .compatible = "rockchip,rk3568-csi-dphy", .data = &rk3568_mipidphy_drv_data, }, + { + .compatible = "rockchip,rk3576-csi-dphy", + .data = &rk3576_mipidphy_drv_data, + }, { .compatible = "rockchip,rk3588-csi-dphy", .data = &rk3588_mipidphy_drv_data, -- 2.43.0