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[2a01:cb00:7c5:9900:d73f:8285:c1e6:47ab]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-49e7d2a94b9sm58001325e9.3.2026.09.15.03.43.30 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 15 Sep 2026 03:43:32 -0700 (PDT) From: Amin Gattout Date: Tue, 15 Sep 2026 12:42:49 +0200 Subject: [PATCH v2 4/4] arm64: dts: rockchip: add csi dphy nodes to rk3576 Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: 7bit Message-Id: <20260915-rk3576-dphy-v2-4-b56e68b54b8c@gmail.com> References: <20260915-rk3576-dphy-v2-0-b56e68b54b8c@gmail.com> In-Reply-To: <20260915-rk3576-dphy-v2-0-b56e68b54b8c@gmail.com> To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Heiko Stuebner , Vinod Koul , Neil Armstrong Cc: Michael Riesch , devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org, linux-kernel@vger.kernel.org, linux-phy@lists.infradead.org, Amin Gattout X-Mailer: b4 0.16.0 X-Developer-Signature: v=1; a=ed25519-sha256; t=1789469006; l=2044; i=amin.gattout@gmail.com; s=20260818; h=from:subject:message-id; bh=bGK8ht4ZsYBRwxHCHXvcjD3xAuJ63yHglUCiy5arzTU=; b=yeWXeDtjlbYXnbnHo+rBAMifURbyetkigWkciYlnmz2Njk1RBaH1wo4bBYUGlJC6lwRWoDU9b tW+D2K+PqmFCxhdXa68gYb5iLmkYhzprkayLva/21NsCifePTjlEZH3 X-Developer-Key: i=amin.gattout@gmail.com; a=ed25519; pk=MSIqDPkCOkwtyP8Fns1m+KFU9SgqoDl2mpLe18vL+hQ= The Rockchip RK3576 features two MIPI CSI-2 DPHYs. Add the device tree nodes for them. Signed-off-by: Amin Gattout --- arch/arm64/boot/dts/rockchip/rk3576.dtsi | 34 ++++++++++++++++++++++++++++++++ 1 file changed, 34 insertions(+) diff --git a/arch/arm64/boot/dts/rockchip/rk3576.dtsi b/arch/arm64/boot/dts/rockchip/rk3576.dtsi index b0c0d3c8b1b1..b7a527614243 100644 --- a/arch/arm64/boot/dts/rockchip/rk3576.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3576.dtsi @@ -973,11 +973,21 @@ sdgmac_grf: syscon@26038000 { reg = <0x0 0x26038000 0x0 0x1000>; }; + csidphy0_grf: syscon@2603a000 { + compatible = "rockchip,rk3576-csidphy-grf", "syscon"; + reg = <0x0 0x2603a000 0x0 0x2000>; + }; + ioc_grf: syscon@26040000 { compatible = "rockchip,rk3576-ioc-grf", "syscon", "simple-mfd"; reg = <0x0 0x26040000 0x0 0xc000>; }; + csidphy1_grf: syscon@2604c000 { + compatible = "rockchip,rk3576-csidphy-grf", "syscon"; + reg = <0x0 0x2604c000 0x0 0x2000>; + }; + cru: clock-controller@27200000 { compatible = "rockchip,rk3576-cru"; reg = <0x0 0x27200000 0x0 0x50000>; @@ -2848,6 +2858,30 @@ hdptxphy: hdmiphy@2b000000 { status = "disabled"; }; + csi_dphy0: phy@2b030000 { + compatible = "rockchip,rk3576-csi-dphy"; + reg = <0x0 0x2b030000 0x0 0x10000>; + clocks = <&cru PCLK_CSIDPHY>; + clock-names = "pclk"; + #phy-cells = <0>; + resets = <&cru SRST_P_CSIPHY>; + reset-names = "apb"; + rockchip,grf = <&csidphy0_grf>; + status = "disabled"; + }; + + csi_dphy1: phy@2b070000 { + compatible = "rockchip,rk3576-csi-dphy"; + reg = <0x0 0x2b070000 0x0 0x10000>; + clocks = <&cru PCLK_CSIDPHY1>; + clock-names = "pclk"; + #phy-cells = <0>; + resets = <&cru SRST_P_CSIDPHY1>; + reset-names = "apb"; + rockchip,grf = <&csidphy1_grf>; + status = "disabled"; + }; + sram: sram@3ff88000 { compatible = "mmio-sram"; reg = <0x0 0x3ff88000 0x0 0x78000>; -- 2.43.0