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Add a binding for the SiTime SiT9531x family of clock generators: an=0A= I2C-controlled device with four independent PLLs, up to eight input=0A= clocks and up to twelve outputs, described as a DPLL provider.=0A= =0A= Signed-off-by: Ali Rouhi =0A= ---=0A= .../bindings/dpll/sitime,sit95316.yaml | 181 ++++++++++++++++++=0A= MAINTAINERS | 6 +=0A= 2 files changed, 187 insertions(+)=0A= create mode 100644 Documentation/devicetree/bindings/dpll/sitime,sit95316.= yaml=0A= =0A= diff --git a/Documentation/devicetree/bindings/dpll/sitime,sit95316.yaml b/= Documentation/devicetree/bindings/dpll/sitime,sit95316.yaml=0A= new file mode 100644=0A= index 000000000000..e71ee3611a83=0A= --- /dev/null=0A= +++ b/Documentation/devicetree/bindings/dpll/sitime,sit95316.yaml=0A= @@ -0,0 +1,181 @@=0A= +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)=0A= +%YAML 1.2=0A= +---=0A= +$id: http://devicetree.org/schemas/dpll/sitime,sit95316.yaml#=0A= +$schema: http://devicetree.org/meta-schemas/core.yaml#=0A= +=0A= +title: SiTime SiT95316/SiT95317 DPLL Clock Generator=0A= +=0A= +maintainers:=0A= + - Ali Rouhi =0A= +=0A= +description: |=0A= + SiTime SiT95316 and SiT95317 are I2C-controlled programmable clock=0A= + generators with integrated DPLL for synchronization applications. Both= =0A= + variants contain four PLLs with automatic/manual reference selection,=0A= + DCO frequency adjustment, and phase offset measurement via an on-chip=0A= + TDC (Time-to-Digital Converter).=0A= +=0A= + Both parts have 4 differential input pairs whose lanes can also be=0A= + driven independently as single-ended references, so 8 inputs are=0A= + individually selectable. SiT95317 drives 8 outputs, SiT95316=0A= + drives 12.=0A= +=0A= +properties:=0A= + compatible:=0A= + enum:=0A= + - sitime,sit95316=0A= + - sitime,sit95317=0A= +=0A= + reg:=0A= + maxItems: 1=0A= +=0A= + clocks:=0A= + maxItems: 1=0A= +=0A= + clock-names:=0A= + items:=0A= + - const: xtal=0A= +=0A= + clock-frequency:=0A= + description:=0A= + XO rate in Hz feeding XIN/XO_CLK. Alternative to the "clocks"=0A= + phandle for platforms where the firmware does not expose the=0A= + oscillator through the clock framework.=0A= +=0A= + reset-gpios:=0A= + maxItems: 1=0A= + description:=0A= + GPIO connected to the chip's active-low reset pin (RESETB).=0A= +=0A= + interrupts:=0A= + maxItems: 1=0A= + description:=0A= + Interrupt from the chip's active-low INTRB output. Asserted when=0A= + the device detects a status change such as lock acquisition or loss.= =0A= +=0A= + sitime,pll-fvco:=0A= + $ref: /schemas/types.yaml#/definitions/uint64-array=0A= + minItems: 4=0A= + maxItems: 4=0A= + description:=0A= + Per-PLL VCO frequency in Hz for PLLA, PLLB, PLLC, PLLD. The=0A= + values exceed 32 bits, which requires an explicit uint64-array=0A= + type; the dtschema meta-schema does not permit a type $ref on a=0A= + "-hz" unit-suffix property (only opp-hz is defined as 64-bit),=0A= + hence no unit suffix. Override where the standard=0A= + Fvco =3D Fref * DIVN derivation does not match the running VCO --=0A= + for example a PLL operating in INTSYNC mode. A value of 0 keeps=0A= + the register-derived computation for that PLL.=0A= +=0A= + sitime,output-pll-map:=0A= + $ref: /schemas/types.yaml#/definitions/uint32-array=0A= + minItems: 8=0A= + maxItems: 12=0A= + items:=0A= + enum: [0, 1, 2, 3, 255]=0A= + description:=0A= + Source PLL index (0=3DPLLA .. 3=3DPLLD) for each output 0..11. The= =0A= + value 255 (0xff) marks an output as unmapped and prevents the=0A= + driver from registering it as a DPLL pin. Override for=0A= + configurations where the chip's per-PLL OUTPUT_ENABLE bitmaps do=0A= + not unambiguously describe output-to-PLL routing.=0A= +=0A= +required:=0A= + - compatible=0A= + - reg=0A= +=0A= +oneOf:=0A= + - required:=0A= + - clocks=0A= + - clock-names=0A= + - required:=0A= + - clock-frequency=0A= +=0A= +allOf:=0A= + - $ref: /schemas/dpll/dpll-device.yaml#=0A= + # SiT95317 exposes 8 outputs, SiT95316 exposes 12. Bound the=0A= + # output-pll-map length to the variant so a SiT95317 node cannot=0A= + # describe more outputs than the part has.=0A= + - if:=0A= + properties:=0A= + compatible:=0A= + contains:=0A= + const: sitime,sit95317=0A= + then:=0A= + properties:=0A= + sitime,output-pll-map:=0A= + maxItems: 8=0A= + # SiT95316 has 12 outputs. When the map is supplied it must describe=0A= + # all of them, otherwise the trailing outputs are left ambiguous.=0A= + - if:=0A= + properties:=0A= + compatible:=0A= + contains:=0A= + const: sitime,sit95316=0A= + then:=0A= + properties:=0A= + sitime,output-pll-map:=0A= + minItems: 12=0A= +=0A= +unevaluatedProperties: false=0A= +=0A= +examples:=0A= + - |=0A= + #include =0A= + #include =0A= +=0A= + i2c {=0A= + #address-cells =3D <1>;=0A= + #size-cells =3D <0>;=0A= +=0A= + dpll@68 {=0A= + compatible =3D "sitime,sit95316";=0A= + reg =3D <0x68>;=0A= + clocks =3D <&xo2>;=0A= + clock-names =3D "xtal";=0A= + reset-gpios =3D <&gpio 78 GPIO_ACTIVE_LOW>;=0A= + interrupts =3D <12 IRQ_TYPE_LEVEL_LOW>;=0A= + dpll-types =3D "eec", "eec", "eec", "eec";=0A= + sitime,pll-fvco =3D /bits/ 64 <6900000000 0 0 0>;=0A= + sitime,output-pll-map =3D <0 0 0 0 0 0 0 0 0 0 0 0>;=0A= +=0A= + input-pins {=0A= + #address-cells =3D <1>;=0A= + #size-cells =3D <0>;=0A= +=0A= + pin@0 {=0A= + reg =3D <0>;=0A= + label =3D "clkin0";=0A= + connection-type =3D "ext";=0A= + supported-frequencies-hz =3D /bits/ 64 <10000000>;=0A= + };=0A= +=0A= + pin@1 {=0A= + reg =3D <1>;=0A= + label =3D "clkin1";=0A= + connection-type =3D "synce";=0A= + supported-frequencies-hz =3D /bits/ 64 <156250000>;=0A= + };=0A= + };=0A= +=0A= + output-pins {=0A= + #address-cells =3D <1>;=0A= + #size-cells =3D <0>;=0A= +=0A= + pin@0 {=0A= + reg =3D <0>;=0A= + label =3D "clkout0";=0A= + esync-control;=0A= + supported-frequencies-hz =3D /bits/ 64 <156250000>;=0A= + };=0A= +=0A= + pin@1 {=0A= + reg =3D <1>;=0A= + label =3D "clkout1";=0A= + supported-frequencies-hz =3D /bits/ 64 <25000000>;=0A= + };=0A= + };=0A= + };=0A= + };=0A= +...=0A= diff --git a/MAINTAINERS b/MAINTAINERS=0A= index 0b42e898f4d8..ef07a53b5fc4 100644=0A= --- a/MAINTAINERS=0A= +++ b/MAINTAINERS=0A= @@ -25157,6 +25157,12 @@ S: Maintained=0A= W: http://www.winischhofer.at/linuxsisusbvga.shtml=0A= F: drivers/usb/misc/sisusbvga/=0A= =0A= +SITIME SIT9531X DPLL DRIVER=0A= +M: Ali Rouhi =0A= +L: netdev@vger.kernel.org=0A= +S: Maintained=0A= +F: Documentation/devicetree/bindings/dpll/sitime,sit95316.yaml=0A= +=0A= SL28 CPLD MFD DRIVER=0A= M: Michael Walle =0A= S: Maintained=0A= -- =0A= 2.39.2 (Apple Git-143)=0A= =0A=