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[199.106.103.52]) by smtp.gmail.com with ESMTPSA id 5a478bee46e88-33ba4fa50e3sm31115791eec.29.2026.09.14.18.56.57 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 14 Sep 2026 18:57:00 -0700 (PDT) From: Shawn Guo To: Bjorn Andersson Cc: Konrad Dybcio , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Bartosz Golaszewski , Krishna Chaitanya Chundru , Yu Zhang , devicetree@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, Konrad Dybcio , Abel Vesa , Bartosz Golaszewski , Shawn Guo Subject: [PATCH v2 2/5] arm64: dts: qcom: nord-rrd: Enable PCIe controllers and PHY Date: Tue, 15 Sep 2026 09:56:29 +0800 Message-ID: <20260915015632.283642-3-shengchao.guo@oss.qualcomm.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260915015632.283642-1-shengchao.guo@oss.qualcomm.com> References: <20260915015632.283642-1-shengchao.guo@oss.qualcomm.com> Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwOTE1MDAyNCBTYWx0ZWRfX9gamDvnkzmn+ NGFTJ8XOqpmbaV+XhF+hUCsYugyTlCf8+l5pNylo0o1AWooiL49vXTpviLJP+55j1EIj8ljOMiC BVk+NgjYYZ9nKdE3bJm647F/ObPOcO0g3AC6gjOHay8fHs/HnsWsK85t+P86te0dsmuyg7+s5Ho 7MzhDYEKTsqP0B+2KCGr6TvO0xUoKa3y3YntZU9X/SDCrJTZSTsMBxvMNDJIbYmNoU5x524DsTB uTkIYWUJC0mrkXF/Goo1pjjz34Jh2ADspRF1EUsCUBOjWo0DyS6VQ2wZlQMv1Yu+SGui2bwLa3I Ko9D3mln+pG7nS5gmOKYdfGJI6kGr6Zk99BTRXuH5DmI0iZtO2muZ29iXxyCexX0SdfSzigt/9R Q6MXSfAUyXFeYZrXf/0ss17ra5p4GcAq1u2tYKUiL8IyqajEW6c1DKE5dXjWyupXgvLL0wdrdkB f39/38JQX+/FyrEjF4g== X-Authority-Analysis: v=2.4 cv=TrFzFzXh c=1 sm=1 tr=0 ts=6aa8a5ee cx=c_pps a=Oh5Dbbf/trHjhBongsHeRQ==:117 a=b9+bayejhc3NMeqCNyeLQQ==:17 a=VdqzKS8jKosA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=_K5XuSEh1TEqbUxoQ0s3:22 a=EUspDBNiAAAA:8 a=f6-OUQb2phOXiqkgZ7QA:9 a=_Vgx9l1VpLgwpw_dHYaR:22 X-Proofpoint-ORIG-GUID: c-K3pkaQgNmJ37iDFLMYctqrhxucFqi8 X-Proofpoint-Spam-Info: AW1haW4tMjYwOTE1MDAyNCBTYWx0ZWRfX1cIQbri19NpU le6K1Cn1llsK2WrVjp2oPBoOEkXeAXAzcXB65tE0YCV0xJMISeeNPb6G9GgfLhH9Jyrpl8na/su Ch3/8V+UAbB3ISv2z+URVjck8hyuhWo= X-Proofpoint-GUID: c-K3pkaQgNmJ37iDFLMYctqrhxucFqi8 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1176,Hydra:6.1.134,FMLib:17.12.100.49 definitions=2026-09-14_05,2026-09-14_02,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 spamscore=0 phishscore=0 priorityscore=1501 lowpriorityscore=0 bulkscore=0 clxscore=1015 suspectscore=0 impostorscore=0 adultscore=0 malwarescore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2609040000 definitions=main-2609150024 From: Krishna Chaitanya Chundru The Nord Robotics Reference Design board routes all four PCIe links, so enable pcie0-pcie3 and the QMP PHY, supply the per-port PHY and PLL rails, and describe the PERST# and WAKE# lines of each root port. Signed-off-by: Krishna Chaitanya Chundru Reviewed-by: Konrad Dybcio Reviewed-by: Abel Vesa Reviewed-by: Bartosz Golaszewski Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/qcom/nord-rrd.dts | 49 +++++++++++++++++++++++++++ 1 file changed, 49 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/nord-rrd.dts b/arch/arm64/boot/dts/qcom/nord-rrd.dts index c547963371b4..4c4d54d7aa90 100644 --- a/arch/arm64/boot/dts/qcom/nord-rrd.dts +++ b/arch/arm64/boot/dts/qcom/nord-rrd.dts @@ -377,6 +377,55 @@ rtc@32 { }; }; +&pcie_phy { + vdda-phy-a-supply = <&vreg_l6a_1p2>; + vdda-phy-b-supply = <&vreg_l4a_1p2>; + vdda-phy-c-supply = <&vreg_l4a_1p2>; + vdda-phy-d-supply = <&vreg_l4a_1p2>; + vdda-pll-a-supply = <&vreg_l1e_0p9>; + vdda-pll-b-supply = <&vreg_l1e_0p9>; + vdda-pll-c-supply = <&vreg_l1e_0p9>; + vdda-pll-d-supply = <&vreg_l1e_0p9>; + + status = "okay"; +}; + +&pcie0 { + status = "okay"; +}; + +&pcie0_port0 { + reset-gpios = <&tlmm 2 GPIO_ACTIVE_LOW>; + wake-gpios = <&tlmm 0 GPIO_ACTIVE_LOW>; +}; + +&pcie1 { + status = "okay"; +}; + +&pcie1_port0 { + reset-gpios = <&tlmm 5 GPIO_ACTIVE_LOW>; + wake-gpios = <&tlmm 3 GPIO_ACTIVE_LOW>; +}; + +&pcie2 { + status = "okay"; +}; + +&pcie2_port0 { + reset-gpios = <&tlmm 8 GPIO_ACTIVE_LOW>; + wake-gpios = <&tlmm 6 GPIO_ACTIVE_LOW>; +}; + +&pcie3 { + status = "okay"; +}; + +&pcie3_port0 { + reset-gpios = <&tlmm 11 GPIO_ACTIVE_LOW>; + wake-gpios = <&tlmm 9 GPIO_ACTIVE_LOW>; +}; + &qupv3_0 { firmware-name = "qcom/nord/qupv3fw.elf"; -- 2.43.0