Re: [PATCH v8 10/13] drm/mediatek: mtk_dsi: Add support for MT8196

[sashiko-bot@kernel.org]

Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider:
- [Medium] drm/mediatek: Incomplete initialization of DSI QoS parameters (missing PREURGENT)
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commit 2eeb791791ca07e53d5c59d273b7795e846f2238
Author: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>

drm/mediatek: mtk_dsi: Add support for MT8196
    
Add support for the new DSI IP found in the Kompanio Ultra MT8196
SoC and its Dimensity and Genio variants.

Differently from the older DSI IPs, the one from MT8196 requires
the initialization of all of the QoS parameters and can make use
of a DSI SRAM reserved buffer (present also on older SoCs but not
mandatory on those).

> diff --git a/drivers/gpu/drm/mediatek/mtk_dsi.c b/drivers/gpu/drm/mediatek/mtk_dsi.c
> index 16bf08bee38e3..6f176515e2587 100644
> --- a/drivers/gpu/drm/mediatek/mtk_dsi.c
> +++ b/drivers/gpu/drm/mediatek/mtk_dsi.c
[ ... ]
> @@ -373,6 +373,59 @@ static const u16 mtk_dsi_regs_mt8186[DSI_ADV_REG_MAX] = {
>  	[DSI_CMDQ] = 0xd00,
>  };
>  
> +static const u16 mtk_dsi_regs_main_v2[DSI_MAIN_REG_MAX] = {
[ ... ]
> +static const u16 mtk_dsi_regs_qos_v2[DSI_QOS_REG_MAX] = {
> +	[DSI_QOS_BUF_CON0] = 0x300,
> +	[DSI_QOS_BUF_CON1] = 0x304,
> +	[DSI_QOS_TX_BUF_RW_TIMES] = 0x310,
> +	[DSI_QOS_SODI_HIGH] = 0x314,
> +	[DSI_QOS_SODI_LOW] = 0x318,
> +	[DSI_QOS_PREULTRA_HIGH] = 0x324,
> +	[DSI_QOS_PREULTRA_LOW] = 0x328,
> +	[DSI_QOS_ULTRA_HIGH] = 0x32c,
> +	[DSI_QOS_ULTRA_LOW] = 0x330,
> +	[DSI_QOS_URGENT_HIGH] = 0x334,
> +	[DSI_QOS_URGENT_LOW] = 0x338,
> +	[DSI_QOS_PREURGENT_HIGH] = 0x33c
> +};

[Severity: Medium]
Is the DSI_QOS_PREURGENT_LOW mapping missing from this array?

The array maps DSI_QOS_PREURGENT_HIGH but completely omits a mapping or enum
definition for DSI_QOS_PREURGENT_LOW. 

Additionally, the commit message explicitly states that the MT8196 IP requires
the initialization of all of the QoS parameters, but it appears PREURGENT
is skipped entirely. 

When the DSI driver probes on SoCs using the new HW buffers and calls
mtk_dsi_config_hw_buffers(), it programs all other QoS thresholds (SODI,
PREULTRA, ULTRA, URGENT) but omits PREURGENT:

drivers/gpu/drm/mediatek/mtk_dsi.c:mtk_dsi_config_hw_buffers() {
    ...
	/* Write all QoS parameters: Screen On Deep Idle, (pre)Ultra, Urgent, RW times */
	mtk_dsi_mask(dsi, reg_qos[DSI_QOS_SODI_HIGH], BUF_THRESHOLD_PARAM, sodi_hi);
	mtk_dsi_mask(dsi, reg_qos[DSI_QOS_SODI_LOW], BUF_THRESHOLD_PARAM, sodi_lo);
	mtk_dsi_mask(dsi, reg_qos[DSI_QOS_PREULTRA_HIGH], BUF_THRESHOLD_PARAM, preultra_hi);
	mtk_dsi_mask(dsi, reg_qos[DSI_QOS_PREULTRA_LOW], BUF_THRESHOLD_PARAM, preultra_lo);
	mtk_dsi_mask(dsi, reg_qos[DSI_QOS_ULTRA_HIGH], BUF_THRESHOLD_PARAM, ultra_hi);
	mtk_dsi_mask(dsi, reg_qos[DSI_QOS_ULTRA_LOW], BUF_THRESHOLD_PARAM, ultra_lo);
	mtk_dsi_mask(dsi, reg_qos[DSI_QOS_URGENT_HIGH], BUF_THRESHOLD_PARAM, urgent_hi);
	mtk_dsi_mask(dsi, reg_qos[DSI_QOS_URGENT_LOW], BUF_THRESHOLD_PARAM, urgent_lo);
	writel(rw_times, dsi->regs + reg_qos[DSI_QOS_TX_BUF_RW_TIMES]);
    ...
}

Could omitting this parameter lead to suboptimal DSI FIFO scheduling, display
artifacts, or underflows, since the hardware configuration is left incomplete?

-- 
Sashiko AI review · https://sashiko.dev/#/patchset/20260915084148.11385-1-angelogioacchino.delregno@collabora.com?part=10