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[79.26.252.140]) by smtp.googlemail.com with ESMTPSA id a640c23a62f3a-c296605b9a6sm587969266b.25.2026.09.15.05.52.32 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 15 Sep 2026 05:52:33 -0700 (PDT) From: Christian Marangi To: Stephen Boyd , Brian Masney , Jerome Brunet , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Christian Marangi , Felix Fietkau , linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v2 1/2] dt-bindings: clock: airoha: Add PHY binding for Serdes port Date: Tue, 15 Sep 2026 14:52:23 +0200 Message-ID: <20260915125226.20579-2-ansuelsmth@gmail.com> X-Mailer: git-send-email 2.53.0 In-Reply-To: <20260915125226.20579-1-ansuelsmth@gmail.com> References: <20260915125226.20579-1-ansuelsmth@gmail.com> Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Add PHY cell property for Serdes port selection. Currently supported only for Airoha AN7581 SoC, that support up to 4 Serdes port. The Serdes port can support both PCIe, USB3 or Ethernet mode. - PCIe1 Serdes can support PCIe or Ethernet mode. - PCIe2 Serdes can support PCIe or Ethernet mode. - USB1 Serdes can support USB3 or HSGMII mode. - USB2 Serdes can support USB3 or PCIe mode. Add bindings to permit correct reference of the Serdes ports in DT. Values are just symbolic and enumerates the Serdes port with a specific number for precise reference. The available Serdes port can be selected following the dt-binding header in [2]. [2] Signed-off-by: Christian Marangi Reviewed-by: Rob Herring (Arm) --- .../bindings/clock/airoha,en7523-scu.yaml | 24 ++++++++++++++++--- include/dt-bindings/soc/airoha,scu-ssr.h | 11 +++++++++ 2 files changed, 32 insertions(+), 3 deletions(-) create mode 100644 include/dt-bindings/soc/airoha,scu-ssr.h diff --git a/Documentation/devicetree/bindings/clock/airoha,en7523-scu.yaml b/Documentation/devicetree/bindings/clock/airoha,en7523-scu.yaml index eb24a5687639..fc37786ac7ed 100644 --- a/Documentation/devicetree/bindings/clock/airoha,en7523-scu.yaml +++ b/Documentation/devicetree/bindings/clock/airoha,en7523-scu.yaml @@ -23,6 +23,7 @@ description: | All these identifiers can be found in: [1]: . + [2]: . The clocks are provided inside a system controller node. @@ -50,6 +51,12 @@ properties: description: ID of the controller reset line const: 1 + '#phy-cells': + description: + The first cell indicates the serdes phy number, see [2] for the + available serdes port. + const: 1 + required: - compatible - reg @@ -65,12 +72,23 @@ allOf: reg: minItems: 2 + '#phy-cells': false + + - if: + properties: + compatible: + const: econet,en751221-scu + then: + properties: + reg: + maxItems: 1 + + '#phy-cells': false + - if: properties: compatible: - enum: - - airoha,en7581-scu - - econet,en751221-scu + const: airoha,en7581-scu then: properties: reg: diff --git a/include/dt-bindings/soc/airoha,scu-ssr.h b/include/dt-bindings/soc/airoha,scu-ssr.h new file mode 100644 index 000000000000..33c64844ada3 --- /dev/null +++ b/include/dt-bindings/soc/airoha,scu-ssr.h @@ -0,0 +1,11 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ + +#ifndef __DT_BINDINGS_AIROHA_SCU_SSR_H +#define __DT_BINDINGS_AIROHA_SCU_SSR_H + +#define AIROHA_SCU_SERDES_PCIE1 0 +#define AIROHA_SCU_SERDES_PCIE2 1 +#define AIROHA_SCU_SERDES_USB1 2 +#define AIROHA_SCU_SERDES_USB2 3 + +#endif /* __DT_BINDINGS_AIROHA_SCU_SSR_H */ -- 2.53.0