Re: [PATCH v2 2/2] clk: en7523: Add support for selecting the Serdes port in SCU

[sashiko-bot@kernel.org]

Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider:
- [High] clk: en7523: en7581_serdes_phy_set_mode() rejects USB Host PHY modes
--

commit e4c0888a17c4cf69587dbf3077fe8a5e2ed19ae7
Author: Christian Marangi <ansuelsmth@gmail.com>

clk: en7523: Add support for selecting the Serdes port in SCU

In the SCU register for clock and reset, there are also some register to
select the Serdes port mode. The Airoha AN7581 SoC have 4 different Serdes
that can switch between PCIe, USB or Ethernet mode.

> diff --git a/drivers/clk/clk-en7523.c b/drivers/clk/clk-en7523.c
> index 5c45aacb6409e..24fdec2e6198c 100644
> --- a/drivers/clk/clk-en7523.c
> +++ b/drivers/clk/clk-en7523.c
[ ... ]
> @@ -847,12 +878,179 @@ static int en7581_reset_register(struct device *dev, void __iomem *base,
[ ... ]
> +	case AIROHA_SCU_SERDES_USB1:
> +		reg = REG_NP_SCU_SSR3;
> +		mask = REG_SSUSB_HSGMII_SEL_MASK;
> +
> +		if (mode != PHY_MODE_ETHERNET && mode != PHY_MODE_USB_DEVICE &&
> +		    mode != PHY_MODE_USB_DEVICE_SS)
> +			return -EINVAL;

[Severity: High]
Does this validation check in en7581_serdes_phy_set_mode() in
drivers/clk/clk-en7523.c incorrectly reject standard USB Host PHY modes for
the USB1 Serdes port?

When a USB controller driver (such as dwc3) is configured in Host mode, it
typically calls phy_set_mode() with PHY_MODE_USB_HOST or PHY_MODE_USB_HOST_SS
during initialization.

Returning -EINVAL here prevents the PHY multiplexer from switching to USB
mode, leaving the Serdes pins disconnected from the USB controller and
breaking USB Host functionality.

Should PHY_MODE_USB_HOST and PHY_MODE_USB_HOST_SS also be allowed here?

> +
> +		if (mode == PHY_MODE_ETHERNET)
> +			sel = REG_SSUSB_HSGMII_SEL_HSGMII;
> +		else
> +			sel = REG_SSUSB_HSGMII_SEL_USB;
> +
> +		break;
> +	case AIROHA_SCU_SERDES_USB2:
> +		reg = REG_NP_SCU_SSTR;
> +		mask = REG_USB_PCIE_SEL_MASK;
> +
> +		if (mode != PHY_MODE_PCIE && mode != PHY_MODE_USB_DEVICE &&
> +		    mode != PHY_MODE_USB_DEVICE_SS)
> +			return -EINVAL;

[Severity: High]
Similarly, does this logic incorrectly reject standard USB Host PHY modes
for the USB2 Serdes port?

If a USB controller initializes in Host or OTG mode, it will request
PHY_MODE_USB_HOST or PHY_MODE_USB_HOST_SS. Without explicitly allowing these
modes, USB Host operations might be completely non-functional on this SoC.

> +
> +		if (mode == PHY_MODE_PCIE)
> +			sel = REG_USB_PCIE_SEL_PCIE;
> +		else
> +			sel = REG_USB_PCIE_SEL_USB;
> +
> +		break;

-- 
Sashiko AI review · https://sashiko.dev/#/patchset/20260915125226.20579-1-ansuelsmth@gmail.com?part=2