From: sashiko-bot@kernel.org
To: "Petko Manolov" <petko.manolov@konsulko.com>
Cc: robh@kernel.org, devicetree@vger.kernel.org, conor+dt@kernel.org
Subject: Re: [PATCH v5 3/3] arm: dts: altera: add Draeger M48 CPU Module
Date: Tue, 15 Sep 2026 13:54:38 +0000 [thread overview]
Message-ID: <20260915135438.F145D1F000FF@smtp.kernel.org> (raw)
In-Reply-To: <20260915133805.3249587-4-petko.manolov@konsulko.com>
Thank you for your contribution! Sashiko AI review found 2 potential issue(s) to consider:
- [High] gpio: dwapb: out-of-bounds MMIO access due to insufficient reg size in gpio nodes
- [Low] dt-bindings: undocumented legacy property m25p,fast-read in QSPI flash node
--
commit e552871800bb6cae08fff136714f65febb16a836
Author: Petko Manolov <petko.manolov@konsulko.com>
arm: dts: altera: add Draeger M48 CPU Module
This commit adds the device tree for the Draeger M48 CPU Module, which is
built around the Altera SoCFPGA.
> diff --git a/arch/arm/boot/dts/intel/socfpga/socfpga_cyclone5_draeger_m48.dts b/arch/arm/boot/dts/intel/socfpga/socfpga_cyclone5_draeger_m48.dts
> new file mode 100644
> index 0000000000000..838708acb31bd
> --- /dev/null
> +++ b/arch/arm/boot/dts/intel/socfpga/socfpga_cyclone5_draeger_m48.dts
[ ... ]
> + soc {
> + gpio3: gpio@ff202000 {
> + #address-cells = <1>;
> + #size-cells = <0>;
> + compatible = "snps,dw-apb-gpio";
> + reg = <0xff202000 0x20>;
[ ... ]
> + gpio4: gpio@ff202020 {
> + #address-cells = <1>;
> + #size-cells = <0>;
> + compatible = "snps,dw-apb-gpio";
> + reg = <0xff202020 0x20>;
[Severity: High]
Can these reg sizes in gpio3 and gpio4 lead to a regression during device
probe?
The snps,dw-apb-gpio driver unconditionally maps the 32-byte region specified
in the DT, but then accesses offset 0x50 (GPIO_EXT_PORTA). This leads to an
out-of-bounds MMIO read/write, potentially causing an external data abort
from the FPGA interconnect.
If the hardware is actually the altr,pio-1.0 controller, which fits in
32 bytes, the wrong compatible string was provided.
[ ... ]
> + flash: flash@0 {
> + #address-cells = <1>;
> + #size-cells = <1>;
> + compatible = "micron,n25q256a", "jedec,spi-nor";
> + reg = <0>;
> +
> + /* chip select */
> + spi-max-frequency = <100000000>;
> + m25p,fast-read;
[Severity: Low]
Does the flash node introduce a regression by using an undocumented legacy
property?
The m25p,fast-read property is deprecated in modern bindings
(jedec,spi-nor.yaml) and causes a dt-schema validation error. Modern device
trees should rely on SFDP auto-discovery or use standard SPI properties.
--
Sashiko AI review · https://sashiko.dev/#/patchset/20260915133805.3249587-1-petko.manolov@konsulko.com?part=3
prev parent reply other threads:[~2026-09-15 13:54 UTC|newest]
Thread overview: 9+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-09-15 13:38 [PATCH v5 0/3] arm: dts: altera: add Draeger M48 CPU Module Petko Manolov
2026-09-15 13:38 ` [PATCH v5 1/3] dt-bindings: vendor-prefixes: add Draeger AG Petko Manolov
2026-09-15 16:29 ` Conor Dooley
2026-09-17 15:13 ` Petko Manolov
2026-09-17 22:11 ` Conor
2026-09-15 13:38 ` [PATCH v5 2/3] dt-bindings: arm: altera: add Draeger M48 Module Petko Manolov
2026-09-15 16:29 ` Conor Dooley
2026-09-15 13:38 ` [PATCH v5 3/3] arm: dts: altera: add Draeger M48 CPU Module Petko Manolov
2026-09-15 13:54 ` sashiko-bot [this message]
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