Re: [PATCH v3 2/2] clk: qcom: Add support for the camera clock controller (CAMCC) on Hawi

[sashiko-bot@kernel.org]

Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider:
- [Medium] clk: qcom: Missing cam_cc_pll7_out_even post-divider and incorrect parent mapping
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commit 08ea08a7c3d2dac0bf07afc4df1ed6bcbe2314f8
Author: Vivek Aknurwar <vivek.aknurwar@oss.qualcomm.com>

clk: qcom: Add support for the camera clock controller (CAMCC) on Hawi

The CAMCC block on the Qualcomm Hawi SoC provides the primary camera clocks.
This patch introduces the driver for the controller, reusing components for
the Camera BIST MCLK and defining clock topologies and PLL configurations.

> diff --git a/drivers/clk/qcom/camcc-hawi.c b/drivers/clk/qcom/camcc-hawi.c
> index 0000000000000..aa52b99aec003 100644
> --- /dev/null
> +++ b/drivers/clk/qcom/camcc-hawi.c
[ ... ]
> +static const struct parent_map cam_cc_parent_map_2[] = {
> +	{ P_BI_TCXO, 0 },
> +	{ P_CAM_CC_PLL0_OUT_MAIN, 1 },
> +	{ P_CAM_CC_PLL0_OUT_EVEN, 2 },
> +	{ P_CAM_CC_PLL0_OUT_ODD, 3 },
> +	{ P_CAM_CC_PLL7_OUT_EVEN, 5 },
> +	{ P_CAM_CC_PLL7_OUT_MAIN, 6 },
> +};
> +
> +static const struct clk_parent_data cam_cc_parent_data_2[] = {
> +	{ .index = DT_BI_TCXO },
> +	{ .hw = &cam_cc_pll0.clkr.hw },
> +	{ .hw = &cam_cc_pll0_out_even.clkr.hw },
> +	{ .hw = &cam_cc_pll0_out_odd.clkr.hw },
> +	{ .hw = &cam_cc_pll7.clkr.hw },
> +	{ .hw = &cam_cc_pll7.clkr.hw },
> +};

[Severity: Medium]
Is the driver missing the cam_cc_pll7_out_even post-divider definition?

In cam_cc_parent_map_2, P_CAM_CC_PLL7_OUT_EVEN corresponds to the 5th element
of the arrays. However, cam_cc_parent_data_2 points this entry to the
undivided cam_cc_pll7.clkr.hw output instead of a divided clock, duplicating
the 6th element meant for P_CAM_CC_PLL7_OUT_MAIN.

If P_CAM_CC_PLL7_OUT_EVEN is selected by a downstream peripheral, this
topology will result in providing the full PLL frequency instead of a divided
clock, which could impact downstream hardware stability.

Would it be appropriate to add the missing clk_alpha_pll_postdiv structure
for cam_cc_pll7_out_even and update the parent data here to point to it?

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Sashiko AI review · https://sashiko.dev/#/patchset/20260915-camcc-hawi-v3-0-5b57f45477f1@oss.qualcomm.com?part=2