From: sashiko-bot@kernel.org
To: "Maíra Canal" <mcanal@igalia.com>
Cc: devicetree@vger.kernel.org, robh@kernel.org,
dri-devel@lists.freedesktop.org, conor+dt@kernel.org
Subject: Re: [PATCH v2 4/4] ARM: dts: bcm2835: Add the V3D reset line
Date: Tue, 15 Sep 2026 21:03:53 +0000 [thread overview]
Message-ID: <20260915210354.41D0F1F000FF@smtp.kernel.org> (raw)
In-Reply-To: <20260915-vc4-reset-control-v2-4-cb3a25b07822@igalia.com>
Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider:
- [Medium] clk: reference leak and underflow in bcm2835_reset_reset via bypassed genpd
--
commit a62442494a68213d73ba03025de353d2162a2d5f
Author: Maíra Canal <mcanal@igalia.com>
ARM: dts: bcm2835: Add the V3D reset line
This commit wires up the V3D reset line to the shared V3D node in the
device tree for BCM2835, BCM2836, and BCM2837. This enables the vc4
driver to use the reset line when recovering from a hang instead of
forcing the power domain down.
> diff --git a/arch/arm/boot/dts/broadcom/bcm2835-common.dtsi b/arch/arm/boot/dts/broadcom/bcm2835-common.dtsi
> index 1e76b290510d3..39eea8ce10583 100644
> --- a/arch/arm/boot/dts/broadcom/bcm2835-common.dtsi
> +++ b/arch/arm/boot/dts/broadcom/bcm2835-common.dtsi
> @@ -139,6 +139,7 @@ v3d: v3d@7ec00000 {
> compatible = "brcm,bcm2835-v3d";
> reg = <0x7ec00000 0x1000>;
> interrupts = <1 10>;
> + resets = <&pm BCM2835_RESET_V3D>;
[Severity: Medium]
Will this reset configuration conflict with the firmware power domain on
Raspberry Pi?
On boards where the V3D device uses a firmware-managed power domain, the
native bcm2835-power genpd is left uninitialized and its native clock
(BCM2835_CLOCK_V3D) enable count is 0.
When the vc4 driver detects a GPU hang, it triggers a reset that calls
into bcm2835_reset_reset(). This unconditionally cycles the native power
domain off and on:
drivers/pmdomain/bcm/bcm2835-power.c:bcm2835_reset_reset() {
...
ret = bcm2835_power_pd_power_off(&pd->base);
...
}
drivers/pmdomain/bcm/bcm2835-power.c:bcm2835_asb_power_off() {
...
clk_disable_unprepare(pd->clk);
...
}
Does calling clk_disable_unprepare() here trigger a kernel WARN_ON by
underflowing the uninitialized 0 count? And subsequently, when the reset
path calls bcm2835_power_pd_power_on(), does clk_prepare_enable()
increment the count from 0 to 1, permanently leaking a clock reference?
--
Sashiko AI review · https://sashiko.dev/#/patchset/20260915-vc4-reset-control-v2-0-cb3a25b07822@igalia.com?part=4
next prev parent reply other threads:[~2026-09-15 21:03 UTC|newest]
Thread overview: 9+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-09-15 20:51 [PATCH v2 0/4] drm/vc4: Reset the V3D block through the reset controller Maíra Canal
2026-09-15 20:51 ` [PATCH v2 1/4] drm/vc4: Drop the undocumented brcm,vc4-v3d compatible Maíra Canal
2026-09-15 20:51 ` [PATCH v2 2/4] dt-bindings: display: bcm2835-v3d: Add an optional reset line Maíra Canal
2026-09-18 8:55 ` Krzysztof Kozlowski
2026-09-15 20:51 ` [PATCH v2 3/4] drm/vc4: Use the reset controller to recover from a GPU hang Maíra Canal
2026-09-15 21:04 ` sashiko-bot
2026-09-15 20:51 ` [PATCH v2 4/4] ARM: dts: bcm2835: Add the V3D reset line Maíra Canal
2026-09-15 21:03 ` sashiko-bot [this message]
2026-09-18 18:55 ` [PATCH v2 0/4] drm/vc4: Reset the V3D block through the reset controller Maíra Canal
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