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Wed, 16 Sep 2026 07:14:59 -0400 From: Janani Sunil Date: Wed, 16 Sep 2026 13:13:55 +0200 Subject: [PATCH v8 06/17] iio: adc: ad7768: Validate master clock rate Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: 7bit Message-ID: <20260916-ad7768-driver-v8-6-27aa24db5225@analog.com> References: <20260916-ad7768-driver-v8-0-27aa24db5225@analog.com> In-Reply-To: <20260916-ad7768-driver-v8-0-27aa24db5225@analog.com> To: =?utf-8?q?Nuno_S=C3=A1?= , Michael Hennerich , Jonathan Cameron , "David Lechner" , Andy Shevchenko , "Rob Herring" , Krzysztof Kozlowski , "Conor Dooley" , Olivier Moysan , Philipp Zabel , Linus Walleij , Bartosz Golaszewski , Jonathan Corbet , Shuah Khan , Michael Walle , Randy Dunlap CC: , , , , , , , =?utf-8?q?Uwe_Kleine-K=C3=B6nig?= , Janani Sunil , Jonathan Cameron , Andy Shevchenko X-Mailer: b4 0.14.3 X-Developer-Signature: v=1; a=ed25519-sha256; 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External CMOS and LVDS clocks support 1.15 MHz to 34 MHz, while a crystal requires 8 MHz to 34 MHz. Reviewed-by: Andy Shevchenko Signed-off-by: Janani Sunil --- drivers/iio/adc/ad7768.c | 24 ++++++++++++++++++++++++ 1 file changed, 24 insertions(+) diff --git a/drivers/iio/adc/ad7768.c b/drivers/iio/adc/ad7768.c index 2c5d0657edf9..7ce0229b5b7c 100644 --- a/drivers/iio/adc/ad7768.c +++ b/drivers/iio/adc/ad7768.c @@ -91,6 +91,9 @@ #define AD7768_SPI_REG_MASK GENMASK(14, 8) #define AD7768_SPI_DATA_MASK GENMASK(7, 0) +#define AD7768_MIN_MCLK_FREQ_HZ (1150 * HZ_PER_KHZ) +#define AD7768_MIN_XTAL_FREQ_HZ (8 * HZ_PER_MHZ) +#define AD7768_MAX_MCLK_FREQ_HZ (34 * HZ_PER_MHZ) #define AD7768_MAX_CHANNEL 8 enum ad7768_clock_source { @@ -810,6 +813,23 @@ static void ad7768_power_off(void *data) dev_err(dev, "Failed to put device to sleep\n"); } +static int ad7768_validate_mclk_rate(struct device *dev, + const struct ad7768_state *st) +{ + unsigned long min_rate = AD7768_MIN_MCLK_FREQ_HZ; + unsigned long rate = clk_get_rate(st->mclk); + + if (st->clock_source == AD7768_CLOCK_SOURCE_XTAL) + min_rate = AD7768_MIN_XTAL_FREQ_HZ; + + if (rate < min_rate || rate > AD7768_MAX_MCLK_FREQ_HZ) + return dev_err_probe(dev, -EINVAL, + "MCLK rate %lu Hz outside %lu-%lu Hz\n", + rate, min_rate, AD7768_MAX_MCLK_FREQ_HZ); + + return 0; +} + static int ad7768_probe(struct spi_device *spi) { unsigned int spi_readback, rev_id; @@ -884,6 +904,10 @@ static int ad7768_probe(struct spi_device *spi) return dev_err_probe(dev, PTR_ERR(st->mclk), "Failed to get master clock\n"); + ret = ad7768_validate_mclk_rate(dev, st); + if (ret) + return ret; + st->regmap = devm_regmap_init(dev, &ad7768_regmap_bus, spi, st->chip_info->regmap_config); if (IS_ERR(st->regmap)) -- 2.43.0