From: Bartosz Golaszewski <bartosz.golaszewski@oss.qualcomm.com>
To: Shawn Guo <shawnguo@kernel.org>,
Bjorn Andersson <andersson@kernel.org>,
Konrad Dybcio <konradybcio@kernel.org>,
Abel Vesa <abelvesa@kernel.org>, Rob Herring <robh@kernel.org>,
Krzysztof Kozlowski <krzk+dt@kernel.org>,
Conor Dooley <conor+dt@kernel.org>,
brgl@kernel.org
Cc: linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org,
linux-kernel@vger.kernel.org,
Bartosz Golaszewski <bartosz.golaszewski@oss.qualcomm.com>
Subject: [PATCH 2/2] arm64: dts: qcom: nord: wire up GPI DMA for QUP I2C/SPI engines
Date: Wed, 16 Sep 2026 17:55:39 +0200 [thread overview]
Message-ID: <20260916-nord-gpi-dts-v1-2-073e3f9c19d0@oss.qualcomm.com> (raw)
In-Reply-To: <20260916-nord-gpi-dts-v1-0-073e3f9c19d0@oss.qualcomm.com>
Add DMA phandles to I2C and SPI QUPv3 serial engine nodes.
Signed-off-by: Bartosz Golaszewski <bartosz.golaszewski@oss.qualcomm.com>
---
arch/arm64/boot/dts/qcom/nord.dtsi | 152 +++++++++++++++++++++++++++++++++++++
1 file changed, 152 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/nord.dtsi b/arch/arm64/boot/dts/qcom/nord.dtsi
index 870033a106db..6152f92ecf38 100644
--- a/arch/arm64/boot/dts/qcom/nord.dtsi
+++ b/arch/arm64/boot/dts/qcom/nord.dtsi
@@ -1098,6 +1098,10 @@ i2c14: i2c@880000 {
reg = <0x0 0x00880000 0x0 0x4000>;
interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>;
+ dmas = <&gpi_dma2 0 0 QCOM_GPI_I2C>,
+ <&gpi_dma2 1 0 QCOM_GPI_I2C>;
+ dma-names = "tx", "rx";
+
#address-cells = <1>;
#size-cells = <0>;
@@ -1109,6 +1113,10 @@ spi14: spi@880000 {
reg = <0x0 0x00880000 0x0 0x4000>;
interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>;
+ dmas = <&gpi_dma2 0 0 QCOM_GPI_SPI>,
+ <&gpi_dma2 1 0 QCOM_GPI_SPI>;
+ dma-names = "tx", "rx";
+
status = "disabled";
};
@@ -1125,6 +1133,10 @@ i2c15: i2c@884000 {
reg = <0x0 0x00884000 0x0 0x4000>;
interrupts = <GIC_SPI 583 IRQ_TYPE_LEVEL_HIGH>;
+ dmas = <&gpi_dma2 0 1 QCOM_GPI_I2C>,
+ <&gpi_dma2 1 1 QCOM_GPI_I2C>;
+ dma-names = "tx", "rx";
+
#address-cells = <1>;
#size-cells = <0>;
@@ -1136,6 +1148,10 @@ spi15: spi@884000 {
reg = <0x0 0x00884000 0x0 0x4000>;
interrupts = <GIC_SPI 583 IRQ_TYPE_LEVEL_HIGH>;
+ dmas = <&gpi_dma2 0 1 QCOM_GPI_SPI>,
+ <&gpi_dma2 1 1 QCOM_GPI_SPI>;
+ dma-names = "tx", "rx";
+
status = "disabled";
};
@@ -1152,6 +1168,10 @@ i2c16: i2c@888000 {
reg = <0x0 0x00888000 0x0 0x4000>;
interrupts = <GIC_SPI 584 IRQ_TYPE_LEVEL_HIGH>;
+ dmas = <&gpi_dma2 0 2 QCOM_GPI_I2C>,
+ <&gpi_dma2 1 2 QCOM_GPI_I2C>;
+ dma-names = "tx", "rx";
+
#address-cells = <1>;
#size-cells = <0>;
@@ -1163,6 +1183,10 @@ spi16: spi@888000 {
reg = <0x0 0x00888000 0x0 0x4000>;
interrupts = <GIC_SPI 584 IRQ_TYPE_LEVEL_HIGH>;
+ dmas = <&gpi_dma2 0 2 QCOM_GPI_SPI>,
+ <&gpi_dma2 1 2 QCOM_GPI_SPI>;
+ dma-names = "tx", "rx";
+
status = "disabled";
};
@@ -1179,6 +1203,10 @@ i2c17: i2c@88c000 {
reg = <0x0 0x0088c000 0x0 0x4000>;
interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>;
+ dmas = <&gpi_dma2 0 3 QCOM_GPI_I2C>,
+ <&gpi_dma2 1 3 QCOM_GPI_I2C>;
+ dma-names = "tx", "rx";
+
#address-cells = <1>;
#size-cells = <0>;
@@ -1190,6 +1218,10 @@ spi17: spi@88c000 {
reg = <0x0 0x0088c000 0x0 0x4000>;
interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>;
+ dmas = <&gpi_dma2 0 3 QCOM_GPI_SPI>,
+ <&gpi_dma2 1 3 QCOM_GPI_SPI>;
+ dma-names = "tx", "rx";
+
status = "disabled";
};
@@ -1206,6 +1238,10 @@ i2c18: i2c@890000 {
reg = <0x0 0x00890000 0x0 0x4000>;
interrupts = <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>;
+ dmas = <&gpi_dma2 0 4 QCOM_GPI_I2C>,
+ <&gpi_dma2 1 4 QCOM_GPI_I2C>;
+ dma-names = "tx", "rx";
+
#address-cells = <1>;
#size-cells = <0>;
@@ -1217,6 +1253,10 @@ spi18: spi@890000 {
reg = <0x0 0x00890000 0x0 0x4000>;
interrupts = <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>;
+ dmas = <&gpi_dma2 0 4 QCOM_GPI_SPI>,
+ <&gpi_dma2 1 4 QCOM_GPI_SPI>;
+ dma-names = "tx", "rx";
+
status = "disabled";
};
@@ -1233,6 +1273,10 @@ i2c19: i2c@894000 {
reg = <0x0 0x00894000 0x0 0x4000>;
interrupts = <GIC_SPI 587 IRQ_TYPE_LEVEL_HIGH>;
+ dmas = <&gpi_dma2 0 5 QCOM_GPI_I2C>,
+ <&gpi_dma2 1 5 QCOM_GPI_I2C>;
+ dma-names = "tx", "rx";
+
#address-cells = <1>;
#size-cells = <0>;
@@ -1244,6 +1288,10 @@ spi19: spi@894000 {
reg = <0x0 0x00894000 0x0 0x4000>;
interrupts = <GIC_SPI 587 IRQ_TYPE_LEVEL_HIGH>;
+ dmas = <&gpi_dma2 0 5 QCOM_GPI_SPI>,
+ <&gpi_dma2 1 5 QCOM_GPI_SPI>;
+ dma-names = "tx", "rx";
+
status = "disabled";
};
@@ -1260,6 +1308,10 @@ i2c20: i2c@898000 {
reg = <0x0 0x00898000 0x0 0x4000>;
interrupts = <GIC_SPI 461 IRQ_TYPE_LEVEL_HIGH>;
+ dmas = <&gpi_dma2 0 6 QCOM_GPI_I2C>,
+ <&gpi_dma2 1 6 QCOM_GPI_I2C>;
+ dma-names = "tx", "rx";
+
#address-cells = <1>;
#size-cells = <0>;
@@ -1271,6 +1323,10 @@ spi20: spi@898000 {
reg = <0x0 0x00898000 0x0 0x4000>;
interrupts = <GIC_SPI 461 IRQ_TYPE_LEVEL_HIGH>;
+ dmas = <&gpi_dma2 0 6 QCOM_GPI_SPI>,
+ <&gpi_dma2 1 6 QCOM_GPI_SPI>;
+ dma-names = "tx", "rx";
+
status = "disabled";
};
@@ -1318,6 +1374,10 @@ i2c0: i2c@980000 {
reg = <0x0 0x00980000 0x0 0x4000>;
interrupts = <GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH>;
+ dmas = <&gpi_dma0 0 0 QCOM_GPI_I2C>,
+ <&gpi_dma0 1 0 QCOM_GPI_I2C>;
+ dma-names = "tx", "rx";
+
#address-cells = <1>;
#size-cells = <0>;
@@ -1329,6 +1389,10 @@ spi0: spi@980000 {
reg = <0x0 0x00980000 0x0 0x4000>;
interrupts = <GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH>;
+ dmas = <&gpi_dma0 0 0 QCOM_GPI_SPI>,
+ <&gpi_dma0 1 0 QCOM_GPI_SPI>;
+ dma-names = "tx", "rx";
+
status = "disabled";
};
@@ -1345,6 +1409,10 @@ i2c1: i2c@984000 {
reg = <0x0 0x00984000 0x0 0x4000>;
interrupts = <GIC_SPI 513 IRQ_TYPE_LEVEL_HIGH>;
+ dmas = <&gpi_dma0 0 1 QCOM_GPI_I2C>,
+ <&gpi_dma0 1 1 QCOM_GPI_I2C>;
+ dma-names = "tx", "rx";
+
#address-cells = <1>;
#size-cells = <0>;
@@ -1356,6 +1424,10 @@ spi1: spi@984000 {
reg = <0x0 0x00984000 0x0 0x4000>;
interrupts = <GIC_SPI 513 IRQ_TYPE_LEVEL_HIGH>;
+ dmas = <&gpi_dma0 0 1 QCOM_GPI_SPI>,
+ <&gpi_dma0 1 1 QCOM_GPI_SPI>;
+ dma-names = "tx", "rx";
+
status = "disabled";
};
@@ -1372,6 +1444,10 @@ i2c2: i2c@988000 {
reg = <0x0 0x00988000 0x0 0x4000>;
interrupts = <GIC_SPI 514 IRQ_TYPE_LEVEL_HIGH>;
+ dmas = <&gpi_dma0 0 2 QCOM_GPI_I2C>,
+ <&gpi_dma0 1 2 QCOM_GPI_I2C>;
+ dma-names = "tx", "rx";
+
#address-cells = <1>;
#size-cells = <0>;
@@ -1383,6 +1459,10 @@ spi2: spi@988000 {
reg = <0x0 0x00988000 0x0 0x4000>;
interrupts = <GIC_SPI 514 IRQ_TYPE_LEVEL_HIGH>;
+ dmas = <&gpi_dma0 0 2 QCOM_GPI_SPI>,
+ <&gpi_dma0 1 2 QCOM_GPI_SPI>;
+ dma-names = "tx", "rx";
+
status = "disabled";
};
@@ -1399,6 +1479,10 @@ i2c3: i2c@98c000 {
reg = <0x0 0x0098c000 0x0 0x4000>;
interrupts = <GIC_SPI 515 IRQ_TYPE_LEVEL_HIGH>;
+ dmas = <&gpi_dma0 0 3 QCOM_GPI_I2C>,
+ <&gpi_dma0 1 3 QCOM_GPI_I2C>;
+ dma-names = "tx", "rx";
+
#address-cells = <1>;
#size-cells = <0>;
@@ -1410,6 +1494,10 @@ spi3: spi@98c000 {
reg = <0x0 0x0098c000 0x0 0x4000>;
interrupts = <GIC_SPI 515 IRQ_TYPE_LEVEL_HIGH>;
+ dmas = <&gpi_dma0 0 3 QCOM_GPI_SPI>,
+ <&gpi_dma0 1 3 QCOM_GPI_SPI>;
+ dma-names = "tx", "rx";
+
status = "disabled";
};
@@ -1426,6 +1514,10 @@ i2c4: i2c@990000 {
reg = <0x0 0x00990000 0x0 0x4000>;
interrupts = <GIC_SPI 516 IRQ_TYPE_LEVEL_HIGH>;
+ dmas = <&gpi_dma0 0 4 QCOM_GPI_I2C>,
+ <&gpi_dma0 1 4 QCOM_GPI_I2C>;
+ dma-names = "tx", "rx";
+
#address-cells = <1>;
#size-cells = <0>;
@@ -1437,6 +1529,10 @@ spi4: spi@990000 {
reg = <0x0 0x00990000 0x0 0x4000>;
interrupts = <GIC_SPI 516 IRQ_TYPE_LEVEL_HIGH>;
+ dmas = <&gpi_dma0 0 4 QCOM_GPI_SPI>,
+ <&gpi_dma0 1 4 QCOM_GPI_SPI>;
+ dma-names = "tx", "rx";
+
status = "disabled";
};
@@ -1453,6 +1549,10 @@ i2c5: i2c@994000 {
reg = <0x0 0x00994000 0x0 0x4000>;
interrupts = <GIC_SPI 517 IRQ_TYPE_LEVEL_HIGH>;
+ dmas = <&gpi_dma0 0 5 QCOM_GPI_I2C>,
+ <&gpi_dma0 1 5 QCOM_GPI_I2C>;
+ dma-names = "tx", "rx";
+
#address-cells = <1>;
#size-cells = <0>;
@@ -1464,6 +1564,10 @@ spi5: spi@994000 {
reg = <0x0 0x00994000 0x0 0x4000>;
interrupts = <GIC_SPI 517 IRQ_TYPE_LEVEL_HIGH>;
+ dmas = <&gpi_dma0 0 5 QCOM_GPI_SPI>,
+ <&gpi_dma0 1 5 QCOM_GPI_SPI>;
+ dma-names = "tx", "rx";
+
status = "disabled";
};
@@ -1511,6 +1615,10 @@ i2c7: i2c@a80000 {
reg = <0x0 0x00a80000 0x0 0x4000>;
interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;
+ dmas = <&gpi_dma1 0 0 QCOM_GPI_I2C>,
+ <&gpi_dma1 1 0 QCOM_GPI_I2C>;
+ dma-names = "tx", "rx";
+
#address-cells = <1>;
#size-cells = <0>;
@@ -1522,6 +1630,10 @@ spi7: spi@a80000 {
reg = <0x0 0x00a80000 0x0 0x4000>;
interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;
+ dmas = <&gpi_dma1 0 0 QCOM_GPI_SPI>,
+ <&gpi_dma1 1 0 QCOM_GPI_SPI>;
+ dma-names = "tx", "rx";
+
status = "disabled";
};
@@ -1538,6 +1650,10 @@ i2c8: i2c@a84000 {
reg = <0x0 0x00a84000 0x0 0x4000>;
interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>;
+ dmas = <&gpi_dma1 0 1 QCOM_GPI_I2C>,
+ <&gpi_dma1 1 1 QCOM_GPI_I2C>;
+ dma-names = "tx", "rx";
+
#address-cells = <1>;
#size-cells = <0>;
@@ -1549,6 +1665,10 @@ spi8: spi@a84000 {
reg = <0x0 0x00a84000 0x0 0x4000>;
interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>;
+ dmas = <&gpi_dma1 0 1 QCOM_GPI_SPI>,
+ <&gpi_dma1 1 1 QCOM_GPI_SPI>;
+ dma-names = "tx", "rx";
+
status = "disabled";
};
@@ -1565,6 +1685,10 @@ i2c9: i2c@a88000 {
reg = <0x0 0x00a88000 0x0 0x4000>;
interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
+ dmas = <&gpi_dma1 0 2 QCOM_GPI_I2C>,
+ <&gpi_dma1 1 2 QCOM_GPI_I2C>;
+ dma-names = "tx", "rx";
+
#address-cells = <1>;
#size-cells = <0>;
@@ -1584,6 +1708,10 @@ i2c10: i2c@a8c000 {
reg = <0x0 0x00a8c000 0x0 0x4000>;
interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>;
+ dmas = <&gpi_dma1 0 3 QCOM_GPI_I2C>,
+ <&gpi_dma1 1 3 QCOM_GPI_I2C>;
+ dma-names = "tx", "rx";
+
#address-cells = <1>;
#size-cells = <0>;
@@ -1603,6 +1731,10 @@ i2c11: i2c@a90000 {
reg = <0x0 0x00a90000 0x0 0x4000>;
interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
+ dmas = <&gpi_dma1 0 4 QCOM_GPI_I2C>,
+ <&gpi_dma1 1 4 QCOM_GPI_I2C>;
+ dma-names = "tx", "rx";
+
#address-cells = <1>;
#size-cells = <0>;
@@ -1614,6 +1746,10 @@ spi11: spi@a90000 {
reg = <0x0 0x00a90000 0x0 0x4000>;
interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
+ dmas = <&gpi_dma1 0 4 QCOM_GPI_SPI>,
+ <&gpi_dma1 1 4 QCOM_GPI_SPI>;
+ dma-names = "tx", "rx";
+
status = "disabled";
};
@@ -1630,6 +1766,10 @@ i2c12: i2c@a94000 {
reg = <0x0 0x00a94000 0x0 0x4000>;
interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>;
+ dmas = <&gpi_dma1 0 5 QCOM_GPI_I2C>,
+ <&gpi_dma1 1 5 QCOM_GPI_I2C>;
+ dma-names = "tx", "rx";
+
#address-cells = <1>;
#size-cells = <0>;
@@ -1641,6 +1781,10 @@ spi12: spi@a94000 {
reg = <0x0 0x00a94000 0x0 0x4000>;
interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>;
+ dmas = <&gpi_dma1 0 5 QCOM_GPI_SPI>,
+ <&gpi_dma1 1 5 QCOM_GPI_SPI>;
+ dma-names = "tx", "rx";
+
status = "disabled";
};
@@ -1657,6 +1801,10 @@ i2c13: i2c@a98000 {
reg = <0x0 0x00a98000 0x0 0x4000>;
interrupts = <GIC_SPI 363 IRQ_TYPE_LEVEL_HIGH>;
+ dmas = <&gpi_dma1 0 6 QCOM_GPI_I2C>,
+ <&gpi_dma1 1 6 QCOM_GPI_I2C>;
+ dma-names = "tx", "rx";
+
#address-cells = <1>;
#size-cells = <0>;
@@ -1668,6 +1816,10 @@ spi13: spi@a98000 {
reg = <0x0 0x00a98000 0x0 0x4000>;
interrupts = <GIC_SPI 363 IRQ_TYPE_LEVEL_HIGH>;
+ dmas = <&gpi_dma1 0 6 QCOM_GPI_SPI>,
+ <&gpi_dma1 1 6 QCOM_GPI_SPI>;
+ dma-names = "tx", "rx";
+
status = "disabled";
};
--
2.47.3
next prev parent reply other threads:[~2026-09-16 15:55 UTC|newest]
Thread overview: 7+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-09-16 15:55 [PATCH 0/2] arm64: dts: qcom: nord: add GPI DMA nodes Bartosz Golaszewski
2026-09-16 15:55 ` [PATCH 1/2] arm64: dts: qcom: nord: add GPI DMA controller nodes Bartosz Golaszewski
2026-09-17 3:46 ` Shawn Guo
2026-09-16 15:55 ` Bartosz Golaszewski [this message]
2026-09-17 3:00 ` [PATCH 0/2] arm64: dts: qcom: nord: add GPI DMA nodes Shawn Guo
2026-09-21 2:11 ` Shawn Guo
2026-09-21 14:31 ` Bartosz Golaszewski
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