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It is compatible with the sm8550 eUSB2 PHY. While at it: On Nord SoC there are three eUSB2 PHYs but only two QUSB2PHY block resets: the HS-only USB20 tile has no dedicated PHY reset and is instead reset as a whole through the controller's own USB20_PRIM_BCR. Make the 'resets' property optional. Signed-off-by: Bartosz Golaszewski Signed-off-by: Shawn Guo --- Documentation/devicetree/bindings/phy/qcom,snps-eusb2-phy.yaml | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/phy/qcom,snps-eusb2-phy.yaml b/Documentation/devicetree/bindings/phy/qcom,snps-eusb2-phy.yaml index 096f6b546632ef8cb83321961c7e5ff261db2b1d..7fe8c82db38d876a9230697103dd9467c49f6c84 100644 --- a/Documentation/devicetree/bindings/phy/qcom,snps-eusb2-phy.yaml +++ b/Documentation/devicetree/bindings/phy/qcom,snps-eusb2-phy.yaml @@ -19,6 +19,7 @@ properties: - enum: - qcom,eliza-snps-eusb2-phy - qcom,milos-snps-eusb2-phy + - qcom,nord-snps-eusb2-phy - qcom,sar2130p-snps-eusb2-phy - qcom,sdx75-snps-eusb2-phy - qcom,sm8650-snps-eusb2-phy @@ -64,7 +65,6 @@ required: - clock-names - vdd-supply - vdda12-supply - - resets additionalProperties: false -- 2.47.3