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Tue, 15 Sep 2026 21:00:10 -0700 (PDT) Received: from wenst-7875.tpe.corp.google.com ([2a00:79e0:203d:7:1f62:7622:5d61:2578]) by smtp.gmail.com with ESMTPSA id 98e67ed59e1d1-39e1b7a3cc9sm2030139a91.14.2026.09.15.21.00.08 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 15 Sep 2026 21:00:09 -0700 (PDT) From: Chen-Yu Tsai To: Matthias Brugger , AngeloGioacchino Del Regno Cc: Chen-Yu Tsai , devicetree@vger.kernel.org, linux-mediatek@lists.infradead.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Icenowy Zheng , YoungJoon Lee Subject: [PATCH RESEND v4 1/2] arm64: dts: mediatek: mt8173: Fix MFG_ASYNC power domain clock Date: Wed, 16 Sep 2026 11:59:51 +0800 Message-ID: <20260916035953.3111607-1-wenst@chromium.org> X-Mailer: git-send-email 2.55.0.1032.g73a4cd73de-goog Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit The MFG_ASYNC domain, which is likely associated to the whole MFG block, currently specifies clk26m as its domain clock. This is bogus, since the clock is an external crystal with no controls. Also, the MFG block has a independent CLK_TOP_AXI_MFG_IN_SEL clock, which according to the block diagram, gates access to the hardware registers. Having this one as the domain clock makes much more sense. This also fixes access to the MFGTOP registers. Change the MFG_ASYNC domain clock to CLK_TOP_AXI_MFG_IN_SEL. Fixes: 8b6562644df9 ("arm64: dts: mediatek: Add mt8173 power domain controller") Reviewed-by: AngeloGioacchino Del Regno Tested-by: Icenowy Zheng Signed-off-by: Chen-Yu Tsai --- arch/arm64/boot/dts/mediatek/mt8173.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/mediatek/mt8173.dtsi b/arch/arm64/boot/dts/mediatek/mt8173.dtsi index b78dbedfeca8..e75ed4bd458f 100644 --- a/arch/arm64/boot/dts/mediatek/mt8173.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8173.dtsi @@ -505,7 +505,7 @@ power-domain@MT8173_POWER_DOMAIN_USB { }; mfg_async: power-domain@MT8173_POWER_DOMAIN_MFG_ASYNC { reg = ; - clocks = <&clk26m>; + clocks = <&topckgen CLK_TOP_AXI_MFG_IN_SEL>; clock-names = "mfg"; #address-cells = <1>; #size-cells = <0>; -- 2.55.0.1032.g73a4cd73de-goog