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Tue, 15 Sep 2026 21:00:12 -0700 (PDT) Received: from wenst-7875.tpe.corp.google.com ([2a00:79e0:203d:7:1f62:7622:5d61:2578]) by smtp.gmail.com with ESMTPSA id 98e67ed59e1d1-39e1b7a3cc9sm2030139a91.14.2026.09.15.21.00.10 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 15 Sep 2026 21:00:12 -0700 (PDT) From: Chen-Yu Tsai To: Matthias Brugger , AngeloGioacchino Del Regno Cc: Chen-Yu Tsai , devicetree@vger.kernel.org, linux-mediatek@lists.infradead.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Icenowy Zheng , YoungJoon Lee Subject: [PATCH RESEND v4 2/2] arm64: dts: mediatek: mt8173: Add GPU device nodes Date: Wed, 16 Sep 2026 11:59:52 +0800 Message-ID: <20260916035953.3111607-2-wenst@chromium.org> X-Mailer: git-send-email 2.55.0.1032.g73a4cd73de-goog In-Reply-To: <20260916035953.3111607-1-wenst@chromium.org> References: <20260916035953.3111607-1-wenst@chromium.org> Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit The MediaTek MT8173 comes with a PowerVR Rogue GX6250, which is part of the Series6XT, another variation of the Rogue family of GPUs. On top of the GPU is a glue layer that handles some clock and power signals. Add device nodes for both. While there is supposed to be two different power domains to the GPU, MediaTek does not have any information on how this is integrated internally. Assign the same GPU power domain to both. Reviewed-by: AngeloGioacchino Del Regno Tested-by: Icenowy Zheng Signed-off-by: Chen-Yu Tsai --- arch/arm64/boot/dts/mediatek/mt8173.dtsi | 31 ++++++++++++++++++++++++ 1 file changed, 31 insertions(+) diff --git a/arch/arm64/boot/dts/mediatek/mt8173.dtsi b/arch/arm64/boot/dts/mediatek/mt8173.dtsi index e75ed4bd458f..66e68702732d 100644 --- a/arch/arm64/boot/dts/mediatek/mt8173.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8173.dtsi @@ -1002,6 +1002,37 @@ u2port1: usb-phy@11291000 { }; }; + gpu: gpu@13000000 { + compatible = "mediatek,mt8173-gpu", "img,img-gx6250", + "img,img-rogue"; + reg = <0 0x13000000 0 0x10000>; + interrupts = ; + clocks = <&mfgtop CLK_MFG_G3D>, + <&mfgtop CLK_MFG_MEM>, + <&mfgtop CLK_MFG_AXI>; + clock-names = "core", "mem", "sys"; + /* + * Binding and GPU core HW have two power domain + * inputs, but MediaTek does not have information + * on how this is done internally. + */ + power-domains = <&mfgtop>, <&mfgtop>; + power-domain-names = "a", "b"; + }; + + mfgtop: clock-controller@13fff000 { + compatible = "mediatek,mt8173-mfgtop"; + reg = <0 0x13fff000 0 0x1000>; + clocks = <&topckgen CLK_TOP_AXI_MFG_IN_SEL>, + <&topckgen CLK_TOP_MEM_MFG_IN_SEL>, + <&topckgen CLK_TOP_MFG_SEL>, + <&clk26m>; + clock-names = "sys", "mem", "core", "clk26m"; + power-domains = <&spm MT8173_POWER_DOMAIN_MFG>; + #clock-cells = <1>; + #power-domain-cells = <0>; + }; + mmsys: syscon@14000000 { compatible = "mediatek,mt8173-mmsys", "syscon"; reg = <0 0x14000000 0 0x1000>; -- 2.55.0.1032.g73a4cd73de-goog