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Fix the wake-gpios polarity by using GPIO_ACTIVE_LOW instead of GPIO_ACTIVE_HIGH. Reviewed-by: Konrad Dybcio Reviewed-by: Manivannan Sadhasivam Signed-off-by: Krishna Chaitanya Chundru --- arch/arm64/boot/dts/qcom/sm8650-ayaneo-pocket-s2.dts | 4 ++-- arch/arm64/boot/dts/qcom/sm8650-hdk.dts | 4 ++-- arch/arm64/boot/dts/qcom/sm8650-mtp.dts | 4 ++-- arch/arm64/boot/dts/qcom/sm8650-qrd.dts | 2 +- 4 files changed, 7 insertions(+), 7 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sm8650-ayaneo-pocket-s2.dts b/arch/arm64/boot/dts/qcom/sm8650-ayaneo-pocket-s2.dts index 6ddf30ecabfe..668c183bc177 100644 --- a/arch/arm64/boot/dts/qcom/sm8650-ayaneo-pocket-s2.dts +++ b/arch/arm64/boot/dts/qcom/sm8650-ayaneo-pocket-s2.dts @@ -1074,7 +1074,7 @@ &mdss_dp0_out { }; &pcie0 { - wake-gpios = <&tlmm 96 GPIO_ACTIVE_HIGH>; + wake-gpios = <&tlmm 96 GPIO_ACTIVE_LOW>; perst-gpios = <&tlmm 94 GPIO_ACTIVE_LOW>; pinctrl-0 = <&pcie0_default_state>; @@ -1108,7 +1108,7 @@ &pcie0_phy { }; &pcie1 { - wake-gpios = <&tlmm 99 GPIO_ACTIVE_HIGH>; + wake-gpios = <&tlmm 99 GPIO_ACTIVE_LOW>; perst-gpios = <&tlmm 97 GPIO_ACTIVE_LOW>; pinctrl-0 = <&pcie1_default_state>; diff --git a/arch/arm64/boot/dts/qcom/sm8650-hdk.dts b/arch/arm64/boot/dts/qcom/sm8650-hdk.dts index 41d0c7edc433..b73ad7861eb4 100644 --- a/arch/arm64/boot/dts/qcom/sm8650-hdk.dts +++ b/arch/arm64/boot/dts/qcom/sm8650-hdk.dts @@ -1027,7 +1027,7 @@ &mdss_dp0 { }; &pcie0 { - wake-gpios = <&tlmm 96 GPIO_ACTIVE_HIGH>; + wake-gpios = <&tlmm 96 GPIO_ACTIVE_LOW>; perst-gpios = <&tlmm 94 GPIO_ACTIVE_LOW>; pinctrl-0 = <&pcie0_default_state>; @@ -1061,7 +1061,7 @@ &pcie0_phy { }; &pcie1 { - wake-gpios = <&tlmm 99 GPIO_ACTIVE_HIGH>; + wake-gpios = <&tlmm 99 GPIO_ACTIVE_LOW>; perst-gpios = <&tlmm 97 GPIO_ACTIVE_LOW>; pinctrl-0 = <&pcie1_default_state>; diff --git a/arch/arm64/boot/dts/qcom/sm8650-mtp.dts b/arch/arm64/boot/dts/qcom/sm8650-mtp.dts index 26045430d34a..1332c864801f 100644 --- a/arch/arm64/boot/dts/qcom/sm8650-mtp.dts +++ b/arch/arm64/boot/dts/qcom/sm8650-mtp.dts @@ -642,7 +642,7 @@ &mdss_dsi0_phy { }; &pcie0 { - wake-gpios = <&tlmm 96 GPIO_ACTIVE_HIGH>; + wake-gpios = <&tlmm 96 GPIO_ACTIVE_LOW>; perst-gpios = <&tlmm 94 GPIO_ACTIVE_LOW>; pinctrl-0 = <&pcie0_default_state>; @@ -659,7 +659,7 @@ &pcie0_phy { }; &pcie1 { - wake-gpios = <&tlmm 99 GPIO_ACTIVE_HIGH>; + wake-gpios = <&tlmm 99 GPIO_ACTIVE_LOW>; perst-gpios = <&tlmm 97 GPIO_ACTIVE_LOW>; pinctrl-0 = <&pcie1_default_state>; diff --git a/arch/arm64/boot/dts/qcom/sm8650-qrd.dts b/arch/arm64/boot/dts/qcom/sm8650-qrd.dts index 1fb78588a504..2e874f046a0e 100644 --- a/arch/arm64/boot/dts/qcom/sm8650-qrd.dts +++ b/arch/arm64/boot/dts/qcom/sm8650-qrd.dts @@ -1021,7 +1021,7 @@ &mdss_dp0 { }; &pcie0 { - wake-gpios = <&tlmm 96 GPIO_ACTIVE_HIGH>; + wake-gpios = <&tlmm 96 GPIO_ACTIVE_LOW>; perst-gpios = <&tlmm 94 GPIO_ACTIVE_LOW>; pinctrl-0 = <&pcie0_default_state>; -- 2.34.1