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Move phys, phy-names, perst-gpios, and wake-gpios from the controller to the existing pcieport0 and newly labeled pcie1_port0 and pcie2_port0, allowing board-level overrides. Rename perst-gpios to reset-gpios to match the binding used in the root port context. Signed-off-by: Krishna Chaitanya Chundru --- arch/arm64/boot/dts/qcom/sm8250.dtsi | 30 ++++++++++++------------------ 1 file changed, 12 insertions(+), 18 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sm8250.dtsi b/arch/arm64/boot/dts/qcom/sm8250.dtsi index e0c357222bc7..caabd201c0d9 100644 --- a/arch/arm64/boot/dts/qcom/sm8250.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8250.dtsi @@ -2207,12 +2207,6 @@ pcie0: pcie@1c00000 { power-domains = <&gcc PCIE_0_GDSC>; - phys = <&pcie0_phy>; - phy-names = "pciephy"; - - perst-gpios = <&tlmm 79 GPIO_ACTIVE_LOW>; - wake-gpios = <&tlmm 81 GPIO_ACTIVE_LOW>; - pinctrl-names = "default"; pinctrl-0 = <&pcie0_default_state>; dma-coherent; @@ -2224,6 +2218,10 @@ pcieport0: pcie@0 { reg = <0x0 0x0 0x0 0x0 0x0>; bus-range = <0x01 0xff>; + phys = <&pcie0_phy>; + reset-gpios = <&tlmm 79 GPIO_ACTIVE_LOW>; + wake-gpios = <&tlmm 81 GPIO_ACTIVE_LOW>; + #address-cells = <3>; #size-cells = <2>; ranges; @@ -2334,12 +2332,6 @@ pcie1: pcie@1c08000 { power-domains = <&gcc PCIE_1_GDSC>; - phys = <&pcie1_phy>; - phy-names = "pciephy"; - - perst-gpios = <&tlmm 82 GPIO_ACTIVE_LOW>; - wake-gpios = <&tlmm 84 GPIO_ACTIVE_LOW>; - pinctrl-names = "default"; pinctrl-0 = <&pcie1_default_state>; dma-coherent; @@ -2351,6 +2343,10 @@ pcie@0 { reg = <0x0 0x0 0x0 0x0 0x0>; bus-range = <0x01 0xff>; + phys = <&pcie1_phy>; + reset-gpios = <&tlmm 82 GPIO_ACTIVE_LOW>; + wake-gpios = <&tlmm 84 GPIO_ACTIVE_LOW>; + #address-cells = <3>; #size-cells = <2>; ranges; @@ -2461,12 +2457,6 @@ pcie2: pcie@1c10000 { power-domains = <&gcc PCIE_2_GDSC>; - phys = <&pcie2_phy>; - phy-names = "pciephy"; - - perst-gpios = <&tlmm 85 GPIO_ACTIVE_LOW>; - wake-gpios = <&tlmm 87 GPIO_ACTIVE_LOW>; - pinctrl-names = "default"; pinctrl-0 = <&pcie2_default_state>; dma-coherent; @@ -2478,6 +2468,10 @@ pcie@0 { reg = <0x0 0x0 0x0 0x0 0x0>; bus-range = <0x01 0xff>; + phys = <&pcie2_phy>; + reset-gpios = <&tlmm 85 GPIO_ACTIVE_LOW>; + wake-gpios = <&tlmm 87 GPIO_ACTIVE_LOW>; + #address-cells = <3>; #size-cells = <2>; ranges; -- 2.34.1