From: sashiko-bot@kernel.org
To: "Francesco Dolcini" <francesco@dolcini.it>
Cc: robh@kernel.org, conor+dt@kernel.org, devicetree@vger.kernel.org,
Frank.Li@kernel.org, imx@lists.linux.dev
Subject: Re: [PATCH v1 2/2] arm64: dts: freescale: Add Toradex OSM iMX95
Date: Thu, 17 Sep 2026 09:52:13 +0000 [thread overview]
Message-ID: <20260917095214.53DFC1F000FF@smtp.kernel.org> (raw)
In-Reply-To: <20260917094217.59508-3-francesco@dolcini.it>
Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider:
- [High] dts: imx95-toradex-osm: pcie1 fails to probe due to shared pinctrl
--
commit abcd097ae33af8abcd2810970c485a8f38372ecf
Author: Antoine Gouby <antoine.gouby@toradex.com>
arm64: dts: freescale: Add Toradex OSM iMX95
This commit adds support for the Toradex OSM iMX95 SoM, based on an NXP
i.MX95 SoC, and its OSM development carrier board.
Link: https://www.toradex.com/computer-on-modules/osm-arm-family/nxp-imx95
Link: https://www.toradex.com/products/carrier-board/osm-development-board
> diff --git a/arch/arm64/boot/dts/freescale/imx95-toradex-osm.dtsi b/arch/arm64/boot/dts/freescale/imx95-toradex-osm.dtsi
> new file mode 100644
> index 0000000000000..c804c32b8fb27
> --- /dev/null
> +++ b/arch/arm64/boot/dts/freescale/imx95-toradex-osm.dtsi
[ ... ]
> +/* OSM PCIE_A */
> +&pcie0 {
> + pinctrl-names = "default";
> + pinctrl-0 = <&pinctrl_pcie_wake>;
> + /* PCIE_A_PERST# (OSM V2) */
> + reset-gpios = <&som_gpio_expander_0 8 GPIO_ACTIVE_LOW>;
> +};
> +
> +/* OSM PCIE_B */
> +&pcie1 {
> + pinctrl-names = "default";
> + pinctrl-0 = <&pinctrl_pcie_wake>;
[Severity: High]
Does this cause the pcie1 probe to unconditionally fail?
The devicetree assigns the pinctrl_pcie_wake group (which contains a single
pin, IMX95_PAD_ENET2_MDIO) to the pinctrl-0 properties of both pcie0 and
pcie1 in imx95-toradex-osm.dtsi.
Since the i.MX/SCMI pinctrl drivers enforce strict exclusive pin ownership,
pcie0 will successfully claim the pin on probe. When pcie1 subsequently
probes, the pinctrl core will reject it with a -EBUSY error because the pin
is already registered to pcie0.
Can this be updated so that both PCIe controllers can probe successfully?
> + /* PCIE_B_PERST# (OSM L33) */
> + reset-gpios = <&som_gpio_expander_0 9 GPIO_ACTIVE_LOW>;
> +};
--
Sashiko AI review · https://sashiko.dev/#/patchset/20260917094217.59508-1-francesco@dolcini.it?part=2
next prev parent reply other threads:[~2026-09-17 9:52 UTC|newest]
Thread overview: 5+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-09-17 9:42 [PATCH v1 0/2] arm64: dts: freescale: Add Toradex OSM iMX95 Francesco Dolcini
2026-09-17 9:42 ` [PATCH v1 1/2] dt-bindings: arm: fsl: " Francesco Dolcini
2026-09-17 9:42 ` [PATCH v1 2/2] arm64: dts: freescale: " Francesco Dolcini
2026-09-17 9:52 ` sashiko-bot [this message]
2026-09-17 10:14 ` [PATCH v1 0/2] " Francesco Dolcini
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