From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mta-65-227.siemens.flowmailer.net (mta-65-227.siemens.flowmailer.net [185.136.65.227]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id BD8564D37DB for ; Thu, 17 Sep 2026 11:05:31 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=185.136.65.227 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1789643143; cv=none; b=JUPjrll6l4zc+hV/6jESMpz3Vpa9zfkOdLTLRVBYVnZb2dUo4zwBsW5J4XjI7inKmhZEhwn05O7tiJEElnRiIwoAlp7flyLysvq1Q5ugkSj3LmhK8r1JRShJxdRCw1KShMIkbCz8EUoOnDlUMpu4Ix8YL4aEjflVhEtj/4ehQnI= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1789643143; c=relaxed/simple; bh=VHbxP4NKlWOtSD5WkpNSfXYZrPAY10l7ujxqWk8ocaY=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=GoXho2COQ/zJORPMU13KkZ37Bju9NchJy83QG1jpr6A6YSOPxYMpVGh1EGsRGFHopLokeZk1QYg/KlwTA66GXtIl8BJCgZY5g/XfVAXtO3HCMTFyCQqXSqHCCH6+XC2LkWIUzf+b6nWwhH3nqRjMGJV/txkl0j3Ai9JWxkYQDto= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=siemens.com; spf=pass smtp.mailfrom=rts-flowmailer.siemens.com; dkim=pass (2048-bit key) header.d=siemens.com header.i=alexander.sverdlin@siemens.com header.b=Cl+yCq84; arc=none smtp.client-ip=185.136.65.227 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=siemens.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=rts-flowmailer.siemens.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=siemens.com header.i=alexander.sverdlin@siemens.com header.b="Cl+yCq84" Received: by mta-65-227.siemens.flowmailer.net with ESMTPSA id 202609171105203a2bf6d3c40002079c for ; Thu, 17 Sep 2026 13:05:20 +0200 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; s=fm1; d=siemens.com; i=alexander.sverdlin@siemens.com; h=Date:From:Subject:To:Message-ID:MIME-Version:Content-Type:Content-Transfer-Encoding:Cc:References:In-Reply-To; bh=MvfE6RVo7N77d1jPZq+4yUexpW1TVNW5JhHuRAUTj6k=; b=Cl+yCq84xzgJwvOh7DKuyayhyAWyV3Lca8I0hMx1xhKhUMS+cugBPqqs4Id6FYQeEbGTr4 91VN9z3PsTacSI3BXRxftiLdwsGqf3LkKzaM1A8Hs9NSqpqD7FPuzo0PF914Nb6otaIfJeuI 3mSaITvNIs0gjXKh+ATZ9SGYXWoB15+ByGhG4bpyqEJR0vsAi5tPWGEqT5/ZmDGkWzRATegV SZb/ySc2vfkPR7tjkoq59meiV4HdpxjqxZfZrnt3hOLeAFdU9a7rlZ/P495eUD3YY39GNpxf IKcKz2agBIYW/eccWHWIJQLdpCZmNGU8UwweyU3ejP32XH5NkpdK4FeA==; From: "A. Sverdlin" To: dri-devel@lists.freedesktop.org, devicetree@vger.kernel.org Cc: Frank Bodammer , Neil Armstrong , Jessica Zhang , David Airlie , Simona Vetter , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Thierry Reding , Sam Ravnborg , linux-kernel@vger.kernel.org, Alexander Sverdlin Subject: [PATCH 2/2] drm/panel: simple: Add support for Truly TFT320240-229-E panel Date: Thu, 17 Sep 2026 13:05:15 +0200 Message-ID: <20260917110517.1053556-3-alexander.sverdlin@siemens.com> In-Reply-To: <20260917110517.1053556-1-alexander.sverdlin@siemens.com> References: <20260917110517.1053556-1-alexander.sverdlin@siemens.com> Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Flowmailer-Platform: Siemens Feedback-ID: 519:519-456497:519-21489:flowmailer From: Frank Bodammer Add display mode and panel descriptor for the Truly TFT320240-229-E LCD panel. Register the panel in the of_device_id table with the compatible string "truly,tft320240-229-e". Signed-off-by: Frank Bodammer Signed-off-by: Alexander Sverdlin --- drivers/gpu/drm/panel/panel-simple.c | 29 ++++++++++++++++++++++++++++ 1 file changed, 29 insertions(+) diff --git a/drivers/gpu/drm/panel/panel-simple.c b/drivers/gpu/drm/panel/panel-simple.c index c95964ba25a95..bd7f6eaeb0deb 100644 --- a/drivers/gpu/drm/panel/panel-simple.c +++ b/drivers/gpu/drm/panel/panel-simple.c @@ -5114,6 +5114,32 @@ static const struct panel_desc tpk_f10a_0102 = { }, }; +static const struct drm_display_mode truly_tft320240_229_e_mode = { + .clock = 6410, + .hdisplay = 320, + .hsync_start = 320 + 8, + .hsync_end = 320 + 8 + 39, + .htotal = 320 + 8 + 39 + 4, + .vdisplay = 240, + .vsync_start = 240 + 8, + .vsync_end = 240 + 8 + 8, + .vtotal = 240 + 8 + 8 + 4, + .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, +}; + +static const struct panel_desc truly_tft320240_229_e = { + .modes = &truly_tft320240_229_e_mode, + .num_modes = 1, + .bpc = 8, + .size = { + .width = 70, + .height = 53, + }, + .bus_format = MEDIA_BUS_FMT_RGB888_1X24, + .bus_flags = DRM_BUS_FLAG_DE_HIGH, + .connector_type = DRM_MODE_CONNECTOR_DPI, +}; + static const struct display_timing urt_umsh_8596md_timing = { .pixelclock = { 33260000, 33260000, 33260000 }, .hactive = { 800, 800, 800 }, @@ -6167,6 +6193,9 @@ static const struct of_device_id platform_of_match[] = { }, { .compatible = "tpk,f10a-0102", .data = &tpk_f10a_0102, + }, { + .compatible = "truly,tft320240-229-e", + .data = &truly_tft320240_229_e, }, { .compatible = "urt,umsh-8596md-t", .data = &urt_umsh_8596md_parallel, -- 2.55.0