Re: [PATCH v2 18/18] arm64: dts: qcom: kodiak: Fix PCIe WAKE# GPIO polarity

[sashiko-bot@kernel.org]

Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider:
- [Medium] dts: undocumented addition of wake-gpios property to pcie1_port0
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commit 6e97f1471613f8cea666aa46eb12ba3627dc0138
Author: Krishna Chaitanya Chundru <krishna.chundru@oss.qualcomm.com>

arm64: dts: qcom: kodiak: Fix PCIe WAKE# GPIO polarity

This commit updates the polarity of the PCIe WAKE# GPIO across several
Qualcomm device trees to match the active-low requirement defined in the
PCIe Base Specification.

> diff --git a/arch/arm64/boot/dts/qcom/qcm6490-particle-tachyon.dts b/arch/arm64/boot/dts/qcom/qcm6490-particle-tachyon.dts
> index 5bb33a8a98304..509fc4941a029 100644
> --- a/arch/arm64/boot/dts/qcom/qcm6490-particle-tachyon.dts
> +++ b/arch/arm64/boot/dts/qcom/qcm6490-particle-tachyon.dts
[ ... ]
> @@ -579,6 +579,7 @@ &pcie1_phy {
>  
>  &pcie1_port0 {
>  	reset-gpios = <&tlmm 2 GPIO_ACTIVE_LOW>;
> +	wake-gpios = <&tlmm 3 GPIO_ACTIVE_LOW>;
>  };

[Severity: Medium]
The commit message states the intent is to fix the polarity of existing
wake-gpios properties by changing GPIO_ACTIVE_HIGH to GPIO_ACTIVE_LOW.
However, for &pcie1_port0 in this file, the wake-gpios property did not
exist previously and is being newly added.

Is this an accidental inclusion, or should the commit message be updated
to clarify that wake functionality is also being added for pcie1_port0
on this board?

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Sashiko AI review · https://sashiko.dev/#/patchset/20260917-root_port-v2-0-0d627d0856d5@oss.qualcomm.com?part=18