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[60.250.196.139]) by smtp.gmail.com with ESMTPSA id 98e67ed59e1d1-39e362e9402sm7969141a91.15.2026.09.17.20.01.34 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 17 Sep 2026 20:01:37 -0700 (PDT) From: Joey Lu To: zhengxingda@iscas.ac.cn, maarten.lankhorst@linux.intel.com, mripard@kernel.org, tzimmermann@suse.de, airlied@gmail.com, simona@ffwll.ch, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org Cc: ychuang3@nuvoton.com, schung@nuvoton.com, yclu4@nuvoton.com, dri-devel@lists.freedesktop.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Joey Lu , Conor Dooley Subject: [PATCH v7 1/7] dt-bindings: display: verisilicon,dc: add support for nuvoton,ma35d1-dcu Date: Fri, 18 Sep 2026 11:01:19 +0800 Message-ID: <20260918030125.315978-2-a0987203069@gmail.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260918030125.315978-1-a0987203069@gmail.com> References: <20260918030125.315978-1-a0987203069@gmail.com> Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Add the Nuvoton MA35D1 DCUltraLite (nuvoton,ma35d1-dcu) to the binding. The DCUltraLite uses only four clocks (core, axi, ahb, pix0) and one reset (core), with a single output port. The MA35D1 clock controller gates the core, AXI and AHB clocks with a single bit, but each remains a distinct clock line feeding the IP with its own rate constraints, so all four must still be listed individually in the devicetree; core, axi and ahb happen to share the same clock phandle. Move the clocks/clock-names minItems to 4 and resets/reset-names minItems to 1 at the top level, since that is the lowest count any supported variant needs. Add an allOf/if block that tightens the constraint back up to the fixed 5-clock/3-reset topology required by the existing thead,th1520-dc8200 compatible, and another one that caps the new nuvoton,ma35d1-dcu compatible at the 4-clock/1-reset count it actually wires up. Restrict the same nuvoton,ma35d1-dcu if block to a single port@0, since the DCUltraLite only has one output port. Signed-off-by: Joey Lu Acked-by: Conor Dooley --- .../bindings/display/verisilicon,dc.yaml | 51 +++++++++++++++++++ 1 file changed, 51 insertions(+) diff --git a/Documentation/devicetree/bindings/display/verisilicon,dc.yaml b/Documentation/devicetree/bindings/display/verisilicon,dc.yaml index 919a900122012..e1e6a3a953646 100644 --- a/Documentation/devicetree/bindings/display/verisilicon,dc.yaml +++ b/Documentation/devicetree/bindings/display/verisilicon,dc.yaml @@ -17,6 +17,7 @@ properties: items: - enum: - thead,th1520-dc8200 + - nuvoton,ma35d1-dcu - const: verisilicon,dc # DC IPs have discoverable ID/revision registers reg: @@ -26,6 +27,7 @@ properties: maxItems: 1 clocks: + minItems: 4 items: - description: DC Core clock - description: DMA AXI bus clock @@ -34,6 +36,7 @@ properties: - description: Pixel clock of output 1 clock-names: + minItems: 4 items: - const: core - const: axi @@ -42,12 +45,14 @@ properties: - const: pix1 resets: + minItems: 1 items: - description: DC Core reset - description: DMA AXI bus reset - description: Configuration AHB bus reset reset-names: + minItems: 1 items: - const: core - const: axi @@ -79,6 +84,52 @@ required: - reset-names - ports +allOf: + - if: + properties: + compatible: + contains: + const: thead,th1520-dc8200 + then: + properties: + clocks: + minItems: 5 + + clock-names: + minItems: 5 + + resets: + minItems: 3 + + reset-names: + minItems: 3 + + - if: + properties: + compatible: + contains: + const: nuvoton,ma35d1-dcu + then: + properties: + clocks: + maxItems: 4 + + clock-names: + maxItems: 4 + + resets: + maxItems: 1 + + reset-names: + maxItems: 1 + + ports: + properties: + port@1: false + + required: + - port@0 + additionalProperties: false examples: -- 2.43.0