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Fri, 18 Sep 2026 02:58:19 -0700 (PDT) Received: from hu-uchheda-hyd.qualcomm.com ([202.46.23.25]) by smtp.gmail.com with ESMTPSA id a92af1059eb24-144ce02b063sm2892970c88.9.2026.09.18.02.58.12 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 18 Sep 2026 02:58:19 -0700 (PDT) From: Umang Chheda To: andersson@kernel.org, konradybcio@kernel.org, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, richardcochran@gmail.com, Borislav Petkov , Catalin Marinas , Will Deacon , Lorenzo Pieralisi , Sudeep Holla , "Rafael J . Wysocki" , Len Brown , Tony Luck , Robin Murphy , Peter Zijlstra , James Morse Cc: linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-edac@vger.kernel.org, Ruidong Tian , umang.chheda@oss.qualcomm.com, avaneesh.dwivedi@oss.qualcomm.com, Faruque Ansari Subject: [PATCH v3 3/5] arm64: dts: qcom: monaco: add RAS error source nodes Date: Fri, 18 Sep 2026 15:27:44 +0530 Message-Id: <20260918095746.3347893-4-umang.chheda@oss.qualcomm.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20260918095746.3347893-1-umang.chheda@oss.qualcomm.com> References: <20260918095746.3347893-1-umang.chheda@oss.qualcomm.com> Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwOTE4MDEzNyBTYWx0ZWRfXwnArSjgBlJeb IXtvrqu0dZ6rNBgJaEfQSMXGcup1UH5FHNPkMs/IPGT75v+3IcM31Ylo6VGVms9hcwO4AFlNPYf e39M1R39sdUemJxM4WMzJiRv9nvm+lfP57WrpyP2B4Wj/uJqg2XFCCiualAHnqVvxFmGBboz3OE 0wjcyHccxwlVj0Pvpo9/KnDaZ7XIuW9rT56JpdMdQlx1wTvtHqAHkr1Qgeomemw5gDmOOsJVd/g y6maYeVqbywrNiLCrnUSb8MbK1ld3i9/dNuKiKNnoMOtNvsLQqW+NAcVaw9rCP+K3kdfzdLU9rz eo6p0Kz88WtXINC/kdViqlihPgFZUnuTddE8cF1BfeialwTBK4a3+LAjPp9LSTZwDcDBKasCwCm pXLS0yTKHpWt6FJO/Y0CmJ8DQ3JsQa7HrVfzq5eMshB+baQ34X5BFFEoJ6sMBseb/xPT92dCBGx eFsm3wdtxV1X9lnNYSw== X-Proofpoint-GUID: KAHKgEFL5NXB90oUmNLVUreYSjBOCL6k X-Authority-Analysis: v=2.4 cv=bcD+w+PB c=1 sm=1 tr=0 ts=6aad0b3d cx=c_pps a=RP+M6JBNLl+fLTcSJhASfg==:117 a=ZePRamnt/+rB5gQjfz0u9A==:17 a=VdqzKS8jKosA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=yx91gb_oNiZeI1HMLzn7:22 a=EUspDBNiAAAA:8 a=KdVUwichBgNWhWzcVTwA:9 a=iS9zxrgQBfv6-_F4QbHw:22 X-Proofpoint-Spam-Info: AW1haW4tMjYwOTE4MDEzNyBTYWx0ZWRfXwuXdSvQVnt12 lH7ZpXmIuo4H0LClVnnH0rrXELlgfZI3mwbKvO5BF+3+3DXKwDl4A86RdE8ZRSl+4Ql2Jm95CAP fZmt55n6JQ45KwQGZJRS6KpBuS98ZX0= X-Proofpoint-ORIG-GUID: KAHKgEFL5NXB90oUmNLVUreYSjBOCL6k X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1176,Hydra:6.1.134,FMLib:17.12.100.49 definitions=2026-09-18_03,2026-09-16_02,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 spamscore=0 clxscore=1015 adultscore=0 suspectscore=0 priorityscore=1501 bulkscore=0 phishscore=0 impostorscore=0 lowpriorityscore=0 malwarescore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2609040000 definitions=main-2609180137 ARM Reliability, Availability and Serviceability (RAS) enables processor components(for eg cache, tlb etc) to record and signal hardware faults through architected error records and fault handling interrupts. This allows software to detect, report and, where possible, recover from hardware errors. The Monaco CPU subsystem implements RAS error records for the L1/L2 cache hierarchy and the shared L3 caches. Describe these error sources in Device Tree so that the ARM RAS framework can discover them and handle cache-related error reports. Co-developed-by: Faruque Ansari Signed-off-by: Faruque Ansari Signed-off-by: Umang Chheda --- arch/arm64/boot/dts/qcom/monaco.dtsi | 30 ++++++++++++++++++++++++++++ 1 file changed, 30 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/monaco.dtsi b/arch/arm64/boot/dts/qcom/monaco.dtsi index 395d32d36844..1728932e52b0 100644 --- a/arch/arm64/boot/dts/qcom/monaco.dtsi +++ b/arch/arm64/boot/dts/qcom/monaco.dtsi @@ -617,6 +617,36 @@ scm: scm { }; }; + l2-cache-error { + compatible = "arm,ras-processor"; + arm,num-records = <1>; + arm,record-impl = /bits/ 64 <0x1>; + arm,status-reporting = /bits/ 64 <0x1>; + arm,cache-ref = <&l2_0>; + interrupts = ; + interrupt-names = "fhi"; + }; + + l3-cluster0-error { + compatible = "arm,ras-processor"; + arm,num-records = <2>; + arm,record-impl = /bits/ 64 <0x2>; + arm,status-reporting = /bits/ 64 <0x2>; + arm,cache-ref = <&l3_0>; + interrupts = ; + interrupt-names = "fhi"; + }; + + l3-cluster1-error { + compatible = "arm,ras-processor"; + arm,num-records = <2>; + arm,record-impl = /bits/ 64 <0x2>; + arm,status-reporting = /bits/ 64 <0x2>; + arm,cache-ref = <&l3_1>; + interrupts = ; + interrupt-names = "fhi"; + }; + memory@80000000 { device_type = "memory"; /* We expect the bootloader to fill in the size */ -- 2.34.1