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Fri, 18 Sep 2026 02:58:35 -0700 (PDT) Received: from hu-uchheda-hyd.qualcomm.com ([202.46.23.25]) by smtp.gmail.com with ESMTPSA id a92af1059eb24-144ce02b063sm2892970c88.9.2026.09.18.02.58.28 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 18 Sep 2026 02:58:35 -0700 (PDT) From: Umang Chheda To: andersson@kernel.org, konradybcio@kernel.org, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, richardcochran@gmail.com, Borislav Petkov , Catalin Marinas , Will Deacon , Lorenzo Pieralisi , Sudeep Holla , "Rafael J . Wysocki" , Len Brown , Tony Luck , Robin Murphy , Peter Zijlstra , James Morse Cc: linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-edac@vger.kernel.org, Ruidong Tian , umang.chheda@oss.qualcomm.com, avaneesh.dwivedi@oss.qualcomm.com, Faruque Ansari Subject: [PATCH v3 5/5] arm64: dts: qcom: shikra: add RAS error source nodes Date: Fri, 18 Sep 2026 15:27:46 +0530 Message-Id: <20260918095746.3347893-6-umang.chheda@oss.qualcomm.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20260918095746.3347893-1-umang.chheda@oss.qualcomm.com> References: <20260918095746.3347893-1-umang.chheda@oss.qualcomm.com> Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwOTE4MDEzNyBTYWx0ZWRfX4NyEE66VuTSr 0njV/gAZulIokvWm50+1cA1ywrLIzOnd6ZxHgsRnsfQQlxVE0bwYMAg3w5wAEwfp7pgSzteCLck GZksLvWaAIixOGchflGOzArevTEVQagtn5cXFI7ERhuTmgOTDIGvc62vyS6zl9LgCdowMeacty1 q6mQWDdBPaxCFioNpX9PNOwbTCCQwaz4Lmv7udo40CN+PSIGe9flepjfzXFvhb+kxQ9L/D5RdmR D2CpFOODXm4XXoV5gn+8a4jslm6fGVAoJv8GYdWoH4A73qIRJUXYH839UDjjy2GQAeg48NNFz1H K7mFOXbodSW75YmrT+4iP3TAYX3pdYc66LhwFiwb3PfAqaHmiVqsA+4u2hS+2HcYoxu5DrUfMcm 8sM0ZuBWFgLzhnKPulrRTO9hRhz2PqURYjyx8qnBS93M+zO5wbvtwYIEKcWth6Hv4SagGxZhG/P CR9PHBNCcOVvAyRGnPw== X-Proofpoint-ORIG-GUID: JMcjOR7SmHWfif-jr5ptkBBJwMry4-TX X-Proofpoint-Spam-Info: AW1haW4tMjYwOTE4MDEzNyBTYWx0ZWRfX8854cqe/v7ET 5tNJegXd3r/xURrYL+D2eTUFTF5ac1NNdGr8qemNhYdcchjoNy/9mJqpZLKBQN+Mwk4iMlDbTS8 Bu0P//v6q5FurUf+hbGUjxzEEdFvz48= X-Authority-Analysis: v=2.4 cv=J9Q/fwnS c=1 sm=1 tr=0 ts=6aad0b4d cx=c_pps a=RP+M6JBNLl+fLTcSJhASfg==:117 a=ZePRamnt/+rB5gQjfz0u9A==:17 a=VdqzKS8jKosA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=_K5XuSEh1TEqbUxoQ0s3:22 a=EUspDBNiAAAA:8 a=a7izLWPGlrKpK18tDBAA:9 a=iS9zxrgQBfv6-_F4QbHw:22 X-Proofpoint-GUID: JMcjOR7SmHWfif-jr5ptkBBJwMry4-TX X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1176,Hydra:6.1.134,FMLib:17.12.100.49 definitions=2026-09-18_03,2026-09-16_02,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 lowpriorityscore=0 adultscore=0 impostorscore=0 clxscore=1015 suspectscore=0 phishscore=0 priorityscore=1501 bulkscore=0 malwarescore=0 spamscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2609040000 definitions=main-2609180137 ARM Reliability, Availability and Serviceability (RAS) enables processor components (for eg cache, tlb etc) to record and signal hardware faults through architected error records and fault handling interrupts. This allows software to detect, report and, where possible, recover from hardware errors. The Shikra CPU subsystem implements RAS error records for the L1/L2 cache hierarchy and the shared L3 caches. Describe these error sources in Device Tree so that the ARM RAS framework can discover them and handle cache-related error reports. Co-developed-by: Faruque Ansari Signed-off-by: Faruque Ansari Signed-off-by: Umang Chheda --- arch/arm64/boot/dts/qcom/shikra.dtsi | 20 ++++++++++++++++++++ 1 file changed, 20 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/shikra.dtsi b/arch/arm64/boot/dts/qcom/shikra.dtsi index c1f06f692f66..c5bbf1f8e46a 100644 --- a/arch/arm64/boot/dts/qcom/shikra.dtsi +++ b/arch/arm64/boot/dts/qcom/shikra.dtsi @@ -330,6 +330,26 @@ opp-2208000000 { }; }; + l2-cache-error { + compatible = "arm,ras-processor"; + arm,num-records = <1>; + arm,record-impl = /bits/ 64 <0x1>; + arm,status-reporting = /bits/ 64 <0x1>; + arm,cache-ref = <&l2_3>; + interrupts = ; + interrupt-names = "fhi"; + }; + + l3-cache-error { + compatible = "arm,ras-processor"; + arm,num-records = <2>; + arm,record-impl = /bits/ 64 <0x2>; + arm,status-reporting = /bits/ 64 <0x2>; + arm,cache-ref = <&l3>; + interrupts = ; + interrupt-names = "fhi"; + }; + modem-etm0 { compatible = "arm,coresight-dummy-source"; -- 2.34.1