Re: [PATCH 3/3] i2c: designware: Add snps,dwc-i2c support and new compatible

[sashiko-bot@kernel.org]

Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider:
- [High] i2c: designware: unintended register write to offset 0x00 for SMBus
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commit 756dafe564a9964f945795b25e2b59168e6adcc6
Author: Aniket Limaye <a-limaye@ti.com>

i2c: designware: Add snps,dwc-i2c support and new compatible

This patch adds register offset tables and bit layouts for the DWC_i2c IP
and registers it with a new MODEL_DWC_I2C flag. It handles variations in
interrupt acknowledgments, timing parameters, and capabilities checking.

> diff --git a/drivers/i2c/busses/i2c-designware-common.c b/drivers/i2c/busses/i2c-designware-common.c
> index a21aeb7f415af..cc05c822aa56d 100644
> --- a/drivers/i2c/busses/i2c-designware-common.c
> +++ b/drivers/i2c/busses/i2c-designware-common.c
> @@ -113,6 +113,41 @@ static const u32 dw_i2c_reg_offsets[DW_REG_IDX_MAX] = {
[ ... ]
> +static const u32 dwc_i2c_reg_offsets[DW_REG_IDX_MAX] = {
> +	[DW_REG_IDX_ENABLE]			= DWC_OPERATION_BLK_OFFSET + 0x04,
> +	[DW_REG_IDX_CAPABILITIES]		= DWC_OPERATION_BLK_OFFSET + 0x0c,
> +	[DW_REG_IDX_CON]			= DWC_I2C_BLK_OFFSET + 0x04,
[ ... ]
> +	[DW_REG_IDX_COMP_VERSION]		= DWC_DEBUG_BLK_OFFSET + 0x08,
> +	[DW_REG_IDX_COMP_TYPE]		= DWC_DEBUG_BLK_OFFSET + 0x0c,
> +};

[Severity: High]
Does this array lack an initialization for DW_REG_IDX_SMBUS_INTR_MASK?

Since this is designated to have the size DW_REG_IDX_MAX, any omitted
indices will default to 0x00.

[ ... ]
> @@ -536,8 +636,10 @@ int i2c_dw_init(struct dw_i2c_dev *dev)
>  	 * Mask SMBus interrupts to block storms from broken
>  	 * firmware that leaves IC_SMBUS=1; the handler never
>  	 * services them.
> +	 * For DWC-i2c, need to first check if SMBus is supported
>  	 */
> -	regmap_write(dev->map, dev->regs[DW_REG_IDX_SMBUS_INTR_MASK], 0);
> +	if (!(dev->flags & MODEL_DWC_I2C) || i2c_dwc_has_smbus(dev))
> +		regmap_write(dev->map, dev->regs[DW_REG_IDX_SMBUS_INTR_MASK], 0);

[Severity: High]
If a DWC_I2C hardware instance actually reports SMBus support via the
capabilities register, i2c_dwc_has_smbus() will return true and this will
attempt to mask the SMBus interrupts.

Because DW_REG_IDX_SMBUS_INTR_MASK is missing from dwc_i2c_reg_offsets,
could this unintendedly write the value 0 to the DWC_I2C block at register
offset 0x00?

Even if the TI TDA54 SoC doesn't support SMBus, this code is reachable for
other SoCs or configurations that might report the capability, which could
lead to unintended configuration changes or bus errors.

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Sashiko AI review · https://sashiko.dev/#/patchset/20260919-tda54-upstream-i2c-v1-0-b0b9f77be18b@ti.com?part=3