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Sun, 20 Sep 2026 00:23:46 -0700 (PDT) Received: from cabron.k.g ([5.203.112.129]) by smtp.gmail.com with ESMTPSA id 4fb4d7f45d1cf-6aa67e3051esm2287839a12.29.2026.09.20.00.23.44 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 20 Sep 2026 00:23:45 -0700 (PDT) Date: Sun, 20 Sep 2026 10:23:43 +0300 From: Petko Manolov To: Krzysztof Kozlowski Cc: linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, dinguyen@kernel.org, arnemaximilian.richter@draeger.com, martynas.grybauskas@draeger.com Subject: Re: [PATCH v6 2/3] dt-bindings: arm: altera: add Draeger M48 Module Message-ID: <20260920072343.GB7878@cabron.k.g> References: <20260917163157.1380860-1-petko.manolov@konsulko.com> <20260917163157.1380860-3-petko.manolov@konsulko.com> <20260918-robust-spotted-orangutan-4b669c@quoll> Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20260918-robust-spotted-orangutan-4b669c@quoll> On 26-09-18 13:55:58, Krzysztof Kozlowski wrote: > On Thu, Sep 17, 2026 at 07:31:55PM +0300, Petko Manolov wrote: > > Add DT compatible string for Draeger's M48 CPU Module that is also based on > > Altera SoCFPGA. > > CPU modules almost never can be alone, thus this is incomplete. You need the > final board compatible. SoM could be a fallback. See NXP bindings how it is > doing for example. Module is perhaps not the best of choice for this board, but to avoid duplicity please read my next reply. Petko